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Release 6.1.10

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This commit is contained in:
Yuxin Zhou
2022-01-29 00:24:03 +00:00
parent b216ceb25e
commit f7f0957188
3111 changed files with 495735 additions and 40800 deletions
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24
ports/cortex_m3/ghs/example_build/sample_threadx.ld
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@@ -19,25 +19,25 @@
-sec
{
.reset 0x000000 :
.picbase 0x1000 :
.text :
.reset 0x000000 :
.picbase 0x1000 :
.text :
.comment :
.intercall :
.interfunc :
.syscall :
.syscall :
.fixaddr :
.fixtype :
.rodata :
.rodata :
.romdata ROM(.data) :
.romsdata ROM(.sdata) :
.secinfo :
.pidbase align(16) :
.sdabase :
.sbss :
.sdata :
.data :
.bss :
.secinfo :
.pidbase align(16) :
.sdabase :
.sbss :
.sdata :
.data :
.bss :
.heap align(16) pad(0x10000) :
.stack align(16) pad(0x1000) :
.free_mem align(16) pad(0x10000) :

24
ports/cortex_m3/ghs/example_build/sample_threadx_el.ld
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@@ -19,25 +19,25 @@
-sec
{
.reset 0x000000 :
.picbase 0x1000 :
.text :
.reset 0x000000 :
.picbase 0x1000 :
.text :
.comment :
.intercall :
.interfunc :
.syscall :
.syscall :
.fixaddr :
.fixtype :
.rodata :
.rodata :
.romdata ROM(.data) :
.romsdata ROM(.sdata) :
.secinfo :
.pidbase align(16) :
.sdabase :
.sbss :
.sdata :
.data :
.bss :
.secinfo :
.pidbase align(16) :
.sdabase :
.sbss :
.sdata :
.data :
.bss :
.heap align(16) pad(0x1000) :
.stack align(16) pad(0x1000) :
.eventlog align(16) pad(0x10000) :

84
ports/cortex_m3/ghs/example_build/tx_initialize_low_level.arm
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@@ -12,8 +12,8 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** ThreadX Component */
/** */
/** Initialize */
/** */
@@ -25,42 +25,42 @@
.text
.align 4
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M3/GHS */
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-M3/GHS */
/* 6.1 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* This function is responsible for any low-level processor */
/* initialization, including setting up interrupt vectors, setting */
/* up a periodic timer interrupt source, saving the system stack */
/* pointer for use in ISR processing later, and finding the first */
/* available RAM memory address for tx_application_define. */
/* */
/* INPUT */
/* */
/* None */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* None */
/* */
/* CALLED BY */
/* */
/* _tx_initialize_kernel_enter ThreadX entry function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@@ -72,7 +72,7 @@
_tx_initialize_low_level:
/* Disable interrupts. */
CPSID i ; Disable interrupts
@@ -80,7 +80,7 @@ _tx_initialize_low_level:
/* _tx_thread_system_stack_ptr = (VOID_PTR) (sp); */
LDR r1,=_tx_thread_system_stack_ptr ; Pickup address of system stack ptr
STR sp, [r1] ; Save system stack
STR sp, [r1] ; Save system stack
/* Save the first available memory address. */
@@ -96,14 +96,14 @@ _tx_initialize_low_level:
LDR r0, =0xE0001000 ; Build address of DWT register
LDR r1, [r0] ; Pickup the current value
ORR r1, r1, 1 ; Set the CYCCNTENA bit
STR r1, [r0] ; Enable the cycle count register
STR r1, [r0] ; Enable the cycle count register
/* Setup Vector Table Offset Register. */
MOV r0, 0xE000E000 ; Build address of NVIC registers
LDR r1, =__vectors ; Pickup address of vector table
STR r1, [r0, 0xD08] ; Set vector table address
STR r1, [r0, 0xD08] ; Set vector table address
/* Configure SysTick for 100Hz clock, or 16384 cycles if no reference. */
@@ -127,7 +127,7 @@ _tx_initialize_low_level:
; Note: PnSV must be lowest priority, which is 0xFF
/* Return to caller. */
BX lr ; Return to caller
.type _tx_initialize_low_level,$function
@@ -138,7 +138,7 @@ _tx_initialize_low_level:
/* Define shells for each of the interrupt vectors. */
.globl __tx_BadHandler
__tx_BadHandler:
__tx_BadHandler:
B __tx_BadHandler
.type __tx_BadHandler,$function
@@ -154,7 +154,7 @@ __tx_IntHandler:
MOV r0, 0 ; Build interrupt code
BL _tx_el_interrupt ; Call interrupt event logging
#endif
; /* Do interrupt handler work here */
; /* .... */
@@ -192,7 +192,7 @@ __tx_SysTickHandler:
.size __tx_SysTickHandler,.-__tx_SysTickHandler
.globl __tx_NMIHandler
.globl __tx_NMIHandler
__tx_NMIHandler:
B __tx_NMIHandler
@@ -213,7 +213,7 @@ __tx_SVCallHandler:
B __tx_SVCallHandler
.type __tx_SVCallHandler,$function
.size __tx_SVCallHandler,.-__tx_SVCallHandler
.size __tx_SVCallHandler,.-__tx_SVCallHandler
/* Reference build options and version ID to ensure they come in. */

42
ports/cortex_m3/ghs/inc/tx_el.h
View File

@@ -12,7 +12,7 @@
/**************************************************************************/
/**************************************************************************/
/** */
/** */
/** ThreadX Component */
/** */
/** ThreadX/GHS Event Log (EL) */
@@ -21,24 +21,24 @@
/**************************************************************************/
/**************************************************************************/
/* */
/* COMPONENT DEFINITION RELEASE */
/* */
/* tx_el.h PORTABLE C/GHS */
/**************************************************************************/
/* */
/* COMPONENT DEFINITION RELEASE */
/* */
/* tx_el.h PORTABLE C/GHS */
/* 6.1 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This file defines the ThreadX event log functions for the GHS MULTI */
/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */
/* */
/* This file defines the ThreadX event log functions for the GHS MULTI */
/* EventAnalyzer. It is assumed that tx_api.h and tx_port.h have */
/* already been included. */
/* */
/* RELEASE HISTORY */
/* */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
@@ -54,16 +54,16 @@
#define TX_EL_VERSION_ID 2 /* Event log version ID */
#define TX_EL_HEADER_SIZE 24 /* Event log header size */
#define TX_EL_TNIS 16 /* Number of thread names supported */
/* If the application needs to */
/* track more thread names, just */
/* increase this number and re- */
/* build the ThreadX library. */
/* If the application needs to */
/* track more thread names, just */
/* increase this number and re- */
/* build the ThreadX library. */
#define TX_EL_TNI_ENTRY_SIZE 44 /* Thread name entries are 44 bytes */
#define TX_EL_TNI_NAME_SIZE 34 /* Thread name size in TNI */
#define TX_EL_NO_MORE_TNI_ROOM 1 /* Error return from thread register*/
#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */
#define TX_EL_NAME_NOT_FOUND 2 /* Error return from un-register */
#define TX_EL_EVENT_SIZE 32 /* Number of bytes in each event */
#define TX_EL_VALID_ENTRY 1 /* Valid log entry */
#define TX_EL_VALID_ENTRY 1 /* Valid log entry */
#define TX_EL_INVALID_ENTRY 0 /* Invalid log entry */
@@ -296,7 +296,7 @@
/* Define filter macros that are inserted in-line with the other macros below. */
#ifdef TX_ENABLE_EVENT_FILTERS
#ifdef TX_ENABLE_EVENT_FILTERS
#define TX_EL_NO_STATUS_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_STATUS_CHANGE)) {
#define TX_EL_NO_INTERRUPT_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_INTERRUPTS)) {
#define TX_EL_NO_THREAD_EVENTS if (!(_tx_el_event_filter & TX_EL_FILTER_THREAD_CALLS)) {
@@ -431,7 +431,7 @@ extern ULONG _tx_el_time_base_lower;
VOID _tx_el_initialize(VOID);
UINT _tx_el_thread_register(TX_THREAD *thread_ptr);
UINT _tx_el_thread_unregister(TX_THREAD *thread_ptr);
VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2,
VOID _tx_el_user_event_insert(UINT sub_type, ULONG info_1, ULONG info_2,
ULONG info_3, ULONG info_4);
VOID _tx_el_thread_running(TX_THREAD *thread_ptr);
VOID _tx_el_thread_preempted(TX_THREAD *thread_ptr);
@@ -748,7 +748,7 @@ VOID _tx_el_event_filter_set(UINT filter);
#define TX_EL_THREAD_UNREGISTER(a) \
_tx_el_thread_unregister(a);
#define TX_EL_INITIALIZE _tx_el_initialize();
#endif
#endif
#else
#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO4(a, b, c, d, e)
#define TX_EL_KERNEL_CALL_EVENT_INSERT_INFO3(a, b, c, d)

68
ports/cortex_m3/ghs/inc/tx_port.h
View File

@@ -26,7 +26,7 @@
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-M3/GHS */
/* 6.1.6 */
/* 6.1.10 */
/* */
/* AUTHOR */
/* */
@@ -48,9 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
@@ -62,7 +62,7 @@
#ifdef TX_INCLUDE_USER_DEFINE_FILE
/* Yes, include the user defines in tx_user.h. The defines in this file may
/* Yes, include the user defines in tx_user.h. The defines in this file may
alternately be defined on the command line. */
#include "tx_user.h"
@@ -113,7 +113,7 @@ typedef unsigned short USHORT;
#define TX_TIMER_THREAD_STACK_SIZE 1024 /* Default timer thread stack size */
#endif
#ifndef TX_TIMER_THREAD_PRIORITY
#ifndef TX_TIMER_THREAD_PRIORITY
#define TX_TIMER_THREAD_PRIORITY 0 /* Default timer thread priority */
#endif
@@ -124,8 +124,8 @@ typedef unsigned short USHORT;
#define TX_INT_ENABLE 0 /* Enable interrupts */
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
/* Define the clock source for trace event entry time stamp. The following two item are port specific.
For example, if the time source is at the address 0x0a800024 and is 16-bits in size, the clock
source constants would be:
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0x0a800024)
@@ -134,7 +134,7 @@ typedef unsigned short USHORT;
*/
#ifndef TX_TRACE_TIME_SOURCE
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004)
#endif
#ifndef TX_TRACE_TIME_MASK
#define TX_TRACE_TIME_MASK 0xFFFFFFFFUL
@@ -146,13 +146,13 @@ typedef unsigned short USHORT;
/* Define the number of ticks per second. This informs the EventAnalyzer what the timestamps
represent. By default, this is set to 1,000,000 i.e., one tick every microsecond. */
#define TX_EL_TICKS_PER_SECOND 1000000
#define TX_EL_TICKS_PER_SECOND 1000000
/* Define the method of how to get the upper and lower 32-bits of the time stamp. By default, simply
simulate the time-stamp source with a counter. */
simulate the time-stamp source with a counter. */
#define read_tbu() _tx_el_time_base_upper
#define read_tbl() ++_tx_el_time_base_lower
#define read_tbu() _tx_el_time_base_upper
#define read_tbl() ++_tx_el_time_base_lower
/* Define the port specific options for the _tx_build_options variable. This variable indicates
@@ -168,7 +168,7 @@ typedef unsigned short USHORT;
#define TX_INLINE_INITIALIZATION
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
/* Determine whether or not stack checking is enabled. By default, ThreadX stack checking is
disabled. When the following is defined, ThreadX thread stack checking is enabled. If stack
checking is enabled (TX_ENABLE_STACK_CHECKING is defined), the TX_DISABLE_STACK_FILLING
define is negated, thereby forcing the stack fill which is necessary for the stack checking
@@ -180,19 +180,19 @@ typedef unsigned short USHORT;
/* Define the TX_THREAD control block extensions for this port. The main reason
for the multiple macros is so that backward compatibility can be maintained with
for the multiple macros is so that backward compatibility can be maintained with
existing ThreadX kernel awareness modules. */
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_0
#define TX_THREAD_EXTENSION_1
#define TX_THREAD_EXTENSION_2 VOID * tx_thread_eh_globals; \
int Errno; /* errno. */ \
char * strtok_saved_pos; /* strtok() position. */
#ifndef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#define TX_THREAD_EXTENSION_3
#define TX_THREAD_EXTENSION_3
#else
#define TX_THREAD_EXTENSION_3 unsigned long long tx_thread_execution_time_total; \
unsigned long long tx_thread_execution_time_last_start;
unsigned long long tx_thread_execution_time_last_start;
#endif
@@ -207,11 +207,11 @@ typedef unsigned short USHORT;
#define TX_TIMER_EXTENSION
/* Define the user extension field of the thread control block. Nothing
/* Define the user extension field of the thread control block. Nothing
additional is needed for this port so it is defined as white space. */
#ifndef TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#define TX_THREAD_USER_EXTENSION
#endif
@@ -241,7 +241,7 @@ typedef unsigned short USHORT;
extern void __tx_cpp_exception_cleanup(TX_THREAD *thread_ptr); \
__tx_cpp_exception_cleanup(thread_ptr); \
}
#else
#else
#define TX_THREAD_DELETE_EXTENSION(thread_ptr) \
{ \
#pragma weak __cpp_exception_cleanup \
@@ -280,7 +280,7 @@ typedef unsigned short USHORT;
/* Define the get system state macro. */
#ifndef TX_THREAD_GET_SYSTEM_STATE
#define TX_THREAD_GET_SYSTEM_STATE() (_tx_thread_system_state | __MRS(__IPSR))
#endif
@@ -292,32 +292,32 @@ typedef unsigned short USHORT;
zero after initialization for Cortex-M ports. */
#ifndef TX_THREAD_SYSTEM_RETURN_CHECK
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#define TX_THREAD_SYSTEM_RETURN_CHECK(c) (c) = ((ULONG) _tx_thread_preempt_disable);
#endif
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
/* Define the macro to ensure _tx_thread_preempt_disable is set early in initialization in order to
prevent early scheduling on Cortex-M parts. */
#define TX_PORT_SPECIFIC_POST_INITIALIZATION _tx_thread_preempt_disable++;
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
/* Determine if the ARM architecture has the CLZ instruction. This is available on
architectures v5 and above. If available, redefine the macro for calculating the
lowest bit set. */
#ifndef TX_DISABLE_INLINE
#define TX_LOWEST_SET_BIT_CALCULATE(m, b) m = m & ((ULONG) (-((LONG) m))); \
b = __CLZ32(m); \
b = 31 - b;
b = 31 - b;
#endif
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
/* Define ThreadX interrupt lockout and restore macros for protection on
access of critical kernel information. The restore interrupt macro must
restore the interrupt posture of the running thread prior to the value
present prior to the disable macro. In most cases, the save area macro
is used to define a local function save area for the disable and restore
macros. */
@@ -327,7 +327,7 @@ typedef unsigned short USHORT;
UINT _tx_thread_interrupt_disable(VOID);
VOID _tx_thread_interrupt_restore(UINT previous_posture);
#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save;
#define TX_INTERRUPT_SAVE_AREA register int interrupt_save;
#define TX_DISABLE interrupt_save = _tx_thread_interrupt_control(TX_INT_DISABLE);
@@ -335,7 +335,7 @@ VOID _tx_thread_interrupt_restore(UIN
#else
#define TX_INTERRUPT_SAVE_AREA register INT interrupt_save;
#define TX_INTERRUPT_SAVE_AREA register int interrupt_save;
/* Define ThreadX interrupt lockout and restore macros using
asm macros. */
@@ -380,7 +380,7 @@ asm void restore_ints(int a)
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.1.9 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-M3/GHS Version 6.1.10 *";
#else
extern CHAR _tx_version_id[];
#endif

2
ports/cortex_m3/ghs/src/tx_thread_interrupt_disable.arm
View File

@@ -82,4 +82,4 @@ _tx_thread_interrupt_disable:
;
;}
.type _tx_thread_interrupt_disable,$function
.size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable
.size _tx_thread_interrupt_disable,.-_tx_thread_interrupt_disable

2
ports/cortex_m3/ghs/src/tx_thread_interrupt_restore.arm
View File

@@ -73,4 +73,4 @@ _tx_thread_interrupt_restore:
;
;}
.type _tx_thread_interrupt_restore,$function
.size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore
.size _tx_thread_interrupt_restore,.-_tx_thread_interrupt_restore

20
ports/cortex_m3/ghs/src/tx_thread_schedule.arm
View File

@@ -28,7 +28,7 @@
;/* FUNCTION RELEASE */
;/* */
;/* _tx_thread_schedule Cortex-M3/GHS */
;/* 6.1.5 */
;/* 6.1.10 */
;/* AUTHOR */
;/* */
;/* William E. Lamie, Microsoft Corporation */
@@ -62,9 +62,9 @@
;/* DATE NAME DESCRIPTION */
;/* */
;/* 09-30-2020 William E. Lamie Initial Version 6.1 */
;/* 03-02-2021 Scott Larson Modified comment(s), add */
;/* 01-31-2022 Scott Larson Modified comment(s), add */
;/* low power code, */
;/* resulting in version 6.1.5 */
;/* resulting in version 6.1.10 */
;/* */
;/**************************************************************************/
;VOID _tx_thread_schedule(VOID)
@@ -111,8 +111,8 @@ PendSV_Handler:
__tx_PendSVHandler:
;
; /* Get current thread value and new thread pointer. */
;
__tx_ts_handler:
;
__tx_ts_handler:
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
;
@@ -130,7 +130,7 @@ __tx_ts_handler:
LDR r1, [r0] ; Pickup current thread pointer
;
; /* Determine if there is a current thread to finish preserving. */
;
;
CBZ r1, __tx_ts_new ; If NULL, skip preservation
;
; /* Recover PSP and preserve current thread context. */
@@ -205,7 +205,7 @@ __tx_ts_restore:
BX lr ; Return to thread!
;
; /* The following is the idle wait processing... in this case, no threads are ready for execution and the
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; system will simply be idle until an interrupt occurs that makes a thread ready. Note that interrupts
; are disabled to allow use of WFI for waiting for a thread to arrive. */
;
__tx_ts_wait:
@@ -235,13 +235,13 @@ __tx_ts_wait:
CPSIE i ; Enable interrupts
B __tx_ts_wait ; Loop to continue waiting
;
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; /* At this point, we have a new thread ready to go. Clear any newly pended PendSV - since we are
; already in the handler! */
;
__tx_ts_ready:
MOV r7, #0x08000000 ; Build clear PendSV value
MOV r8, #0xE000E000 ; Build base NVIC address
STR r7, [r8, #0xD04] ; Clear any PendSV
STR r7, [r8, #0xD04] ; Clear any PendSV
;
; /* Re-enable interrupts and restore new thread. */
;
@@ -250,4 +250,4 @@ __tx_ts_ready:
;}
;
.type __tx_PendSVHandler,$function
.size __tx_PendSVHandler,.-__tx_PendSVHandler
.size __tx_PendSVHandler,.-__tx_PendSVHandler

2
ports/cortex_m3/ghs/src/tx_thread_system_return.arm
View File

@@ -81,7 +81,7 @@ _tx_thread_system_return:
CPSIE i ; Enable interrupts
MSR PRIMASK, r1 ; Restore original interrupt posture
_isr_context:
BX lr ; Return to caller
BX lr ; Return to caller
;}
.type _tx_thread_system_return,$function
.size _tx_thread_system_return,.-_tx_thread_system_return

6
ports/cortex_m3/ghs/src/tx_timer_interrupt.arm
View File

@@ -84,7 +84,7 @@ _tx_timer_interrupt:
; if (_tx_timer_time_slice)
; {
;
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r3, =_tx_timer_time_slice ; Pickup address of time-slice
LDR r2, [r3, #0] ; Pickup time-slice
CBZ r2, __tx_timer_no_time_slice ; Is it non-active?
; Yes, skip time-slice processing
@@ -201,13 +201,13 @@ __tx_timer_dont_activate:
; if (_tx_timer_expired_time_slice)
; {
;
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r3, =_tx_timer_expired_time_slice ; Pickup addr of time-slice expired
LDR r2, [r3, #0] ; Pickup the actual flag
CBZ r2, __tx_timer_not_ts_expiration ; See if the flag is set
; No, skip time-slice processing
;
; /* Time slice interrupted thread. */
; _tx_thread_time_slice();
; _tx_thread_time_slice();
BL _tx_thread_time_slice ; Call time-slice processing
LDR r0, =_tx_thread_preempt_disable ; Build address of preempt disable flag