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Release 6.1.10

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This commit is contained in:
Yuxin Zhou
2022-01-29 00:24:03 +00:00
parent b216ceb25e
commit f7f0957188
3111 changed files with 495735 additions and 40800 deletions
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21
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/GICv3_gicr.c
View File

@@ -1,7 +1,7 @@
/*
* GICv3_gicr.c - generic driver code for GICv3 redistributor
*
* Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
* Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
@@ -129,6 +129,25 @@ static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
/**********************************************************************/
// This function walks a block of RDs to find one with the matching affinity
uint32_t GetGICR(uint32_t affinity)
{
GICv3_redistributor_RD* gicr;
uint32_t index = 0;
do
{
gicr = getgicrRD(index);
if (gicr->GICR_TYPER[1] == affinity)
return index;
index++;
}
while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
return 0xFFFFFFFF; // return -1 to signal not RD found
}
void WakeupGICR(uint32_t gicr)
{
GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);

49
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.S
View File

@@ -1,7 +1,8 @@
//
// Armv8-A AArch64 - Basic Mutex Example
// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -43,6 +44,7 @@ _mutex_initialize:
ret
.cfi_endproc
#if !defined(USE_LSE_ATOMIC)
.type _mutex_acquire, "function"
.cfi_startproc
@@ -84,3 +86,48 @@ _mutex_release:
stlr w1, [x0]
ret
.cfi_endproc
#else // LSE version
.type _mutex_acquire, "function"
.cfi_startproc
_mutex_acquire:
// This uses a "ticket lock". The lock is stored as a 32-bit value:
// - the upper 16-bits record the thread's ticket number ("take a ticket")
// - the lower 16-bits record the ticket being served ("now serving")
// atomically load then increment the thread's ticket number ("take a ticket")
mov w3, #(1 << 16)
ldadda w3, w1, [x0]
// is the ticket now being served?
eor w2, w1, w1, ror #16
cbz w2, loop_exit
// no, so wait for the ticket to be served
// send a local event to avoid missing an unlock before the exclusive load
sevl
loop:
wfe
ldaxrh w3, [x0]
eor w2, w3, w1, lsr #16
cbnz w2, loop
//
// OK, we have the mutex, our work is done here
//
loop_exit:
ret
.cfi_endproc
.type _mutex_release, "function"
.cfi_startproc
_mutex_release:
mov w1, #1
staddlh w1, [x0]
ret
.cfi_endproc
#endif

66
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/MP_Mutexes.h Normal file
View File

@@ -0,0 +1,66 @@
/*
* Armv8-A AArch64 - Basic Mutex Example
*
* Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef MP_MUTEX_H
#define MP_MUTEX_H
/*
* The Arm C library calls-out to these functions to manage multithreading.
* They can also be called by user application code.
*
* Mutex type is specified by the Arm C library
*
* Declare function prototypes for libc mutex routines
*/
typedef signed int *mutex;
/*
* int _mutex_initialize(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* 0 - application is non-threaded
* 1 - application is threaded
* The C library uses the return result to indicate whether it is being used in a multithreaded environment.
*/
int _mutex_initialize(mutex *m);
/*
* void _mutex_acquire(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* <nothing>
*
* Side Effects
* Routine does not return until the mutex has been claimed. A load-acquire
* is used to guarantee that the mutex claim is properly ordered with
* respect to any accesses to the resource protected by the mutex
*/
void _mutex_acquire(mutex *m);
/*
* void _mutex_release(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* <nothing>
*
* Side Effects
* A store-release is used to guarantee that the mutex release is properly
* ordered with respect any accesses to the resource protected by the mutex
*/
void _mutex_release(mutex *m);
#endif

22
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c
View File

@@ -3,19 +3,22 @@
byte pool, and block pool. */
#include "tx_api.h"
#include <stddef.h>
extern void init_timer(void); /* in timer_interrupts.c */
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 0x20000
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define a memory area to create a byte pool in. */
/* Define byte pool memory. */
UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE];
UCHAR memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8)));
/* Define the ThreadX object control blocks... */
@@ -68,6 +71,8 @@ UCHAR event_buffer[65536];
#endif
/* Define main entry point. */
int main(void)
{
@@ -95,7 +100,7 @@ CHAR *pointer = TX_NULL;
#endif
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
@@ -386,4 +391,3 @@ UINT status;
break;
}
}

80
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.launch
View File

@@ -6,17 +6,17 @@
<stringAttribute key="ANDROID_PROCESS_NAME" value=""/>
<mapAttribute key="AverageDurationTracker">
<mapEntry key="*Fetching Data" value="34126331"/>
<mapEntry key="*Fetching Data Model" value="1439173"/>
<mapEntry key="*Fetching Data Model" value="1887986"/>
<mapEntry key="*FunctionLoader" value="137168653"/>
<mapEntry key="*list global low level symbols" value="2707112"/>
<mapEntry key="*list global low level symbols" value="3163826"/>
<mapEntry key="*loading memory from target" value="2367919"/>
<mapEntry key="*loading values from target" value="8477514"/>
<mapEntry key="*loading values from target" value="8665557"/>
<mapEntry key="*trace" value="1527238"/>
<mapEntry key="*updating expressions" value="101886453"/>
<mapEntry key="*updating expressions" value="25251903"/>
<mapEntry key="*updating local_variables" value="836905"/>
<mapEntry key="*updating registers" value="97090462"/>
<mapEntry key="*updating variables" value="877039"/>
<mapEntry key="AddEventObserver" value="6587743"/>
<mapEntry key="AddEventObserver" value="5292071"/>
<mapEntry key="Evaluate" value="1689813"/>
<mapEntry key="ResumeToHere" value="20159012"/>
<mapEntry key="Retrieving globals list" value="21298708"/>
@@ -24,11 +24,11 @@
<mapEntry key="backtrace" value="21505977"/>
<mapEntry key="break" value="9764564"/>
<mapEntry key="checking tracepoints" value="372731"/>
<mapEntry key="compute execution mode" value="557345"/>
<mapEntry key="compute execution mode" value="835755"/>
<mapEntry key="console" value="11946310"/>
<mapEntry key="continue" value="12697403"/>
<mapEntry key="continue" value="21247618"/>
<mapEntry key="core" value="5451456"/>
<mapEntry key="directory" value="4737162"/>
<mapEntry key="directory" value="4479981"/>
<mapEntry key="disable" value="2444670"/>
<mapEntry key="disassemble" value="64135505"/>
<mapEntry key="enable" value="5445745"/>
@@ -36,40 +36,41 @@
<mapEntry key="evaluate address" value="1056014"/>
<mapEntry key="finish" value="20115248"/>
<mapEntry key="get byte order" value="633302"/>
<mapEntry key="get capabilities" value="548556"/>
<mapEntry key="get execution addresss" value="438164"/>
<mapEntry key="get source lines" value="3151194"/>
<mapEntry key="get substitute paths" value="293110"/>
<mapEntry key="get capabilities" value="382078"/>
<mapEntry key="get execution addresss" value="403253"/>
<mapEntry key="get source lines" value="951928"/>
<mapEntry key="get substitute paths" value="523052"/>
<mapEntry key="getValidEncodings" value="1202320"/>
<mapEntry key="initialize command help" value="68196070"/>
<mapEntry key="initialize command help" value="63855085"/>
<mapEntry key="interrupt" value="11210435"/>
<mapEntry key="list breakpoint options" value="1264804"/>
<mapEntry key="list breakpoints" value="1473749"/>
<mapEntry key="list instruction sets" value="1512051"/>
<mapEntry key="list signals" value="1314040"/>
<mapEntry key="list breakpoint options" value="2030851"/>
<mapEntry key="list breakpoints" value="1627224"/>
<mapEntry key="list instruction sets" value="1847125"/>
<mapEntry key="list signals" value="1953020"/>
<mapEntry key="list source files" value="573423"/>
<mapEntry key="list watchpoint options" value="4130737"/>
<mapEntry key="list watchpoints" value="739118"/>
<mapEntry key="loadfile" value="308178719"/>
<mapEntry key="list watchpoint options" value="6057468"/>
<mapEntry key="list watchpoints" value="970059"/>
<mapEntry key="loadfile" value="386648009"/>
<mapEntry key="next" value="24266800"/>
<mapEntry key="query supports threads" value="215433"/>
<mapEntry key="remove" value="3597385"/>
<mapEntry key="run script" value="37326822"/>
<mapEntry key="set CWD" value="4366642"/>
<mapEntry key="remove" value="7663692"/>
<mapEntry key="run script" value="44460661"/>
<mapEntry key="set CWD" value="5180571"/>
<mapEntry key="set breakpoint properties" value="10666013"/>
<mapEntry key="set debug-from" value="1215725"/>
<mapEntry key="set substitute-path" value="23083827"/>
<mapEntry key="source use_model_semihosting.ds" value="7540462"/>
<mapEntry key="start" value="36728254"/>
<mapEntry key="set debug-from" value="1157012"/>
<mapEntry key="set substitute-path" value="27245163"/>
<mapEntry key="source use_model_semihosting.ds" value="8849881"/>
<mapEntry key="start" value="50528177"/>
<mapEntry key="step" value="26461127"/>
<mapEntry key="stepi" value="29574773"/>
<mapEntry key="synchronizing trace ranges" value="21582"/>
<mapEntry key="target reset" value="32992642"/>
<mapEntry key="toggleBreakpoint" value="7875634"/>
<mapEntry key="toggleBreakpoint" value="19462208"/>
<mapEntry key="updateBreakpointLocation" value="1868000"/>
<mapEntry key="waitForTargetToStop" value="47515299"/>
<mapEntry key="waitForTargetToStop" value="52570549"/>
<mapEntry key="write expression" value="21220700"/>
</mapAttribute>
<stringAttribute key="CLOCK_SPEED" value="Auto"/>
<listAttribute key="DEBUG_TAB."/>
<stringAttribute key="DEBUG_TAB..RESOURCES.0.TYPE" value="SOURCE_DIR"/>
<stringAttribute key="DEBUG_TAB..RESOURCES.0.VALUE" value="${workspace_loc:/sample_threadx}"/>
@@ -89,15 +90,15 @@
<stringAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.0.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_ANDROID.RESOURCES.COUNT" value="1"/>
<listAttribute key="FILES.DEBUG_RESIDENT_APP"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.TYPE" value="APPLICATION_ON_TARGET"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="APPLICATION_ON_TARGET"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.1.VALUE" value=""/>
<intAttribute key="FILES.DEBUG_RESIDENT_APP.RESOURCES.COUNT" value="2"/>
<listAttribute key="FILES.DOWNLOAD_AND_DEBUG"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
@@ -105,13 +106,13 @@
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_AND_DEBUG.RESOURCES.COUNT" value="3"/>
<listAttribute key="FILES.DOWNLOAD_DEBUG"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.0.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.OPTION.ON_DEMAND_LOAD" value="true"/>
@@ -119,7 +120,7 @@
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.1.VALUE" value=""/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ALSO_LOAD_SYMBOLS" value="false"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.OPTION.ON_DEMAND_LOAD" value="true"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_DOWNLOAD_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.TYPE" value="TARGET_WORKING_DIR"/>
<stringAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.2.VALUE" value=""/>
<intAttribute key="FILES.DOWNLOAD_DEBUG.RESOURCES.COUNT" value="3"/>
<intAttribute key="FILES.DOWNLOAD_DEBUG_ANDROID.RESOURCES.COUNT" value="0"/>
@@ -162,6 +163,8 @@
<intAttribute key="POST_TRIGGER_CAPTURE_SIZE" value="50"/>
<booleanAttribute key="RSE_USE_HOSTNAME" value="true"/>
<booleanAttribute key="STOP_ON_TRIGGER" value="false"/>
<booleanAttribute key="SWD" value="false"/>
<booleanAttribute key="SWJ" value="true"/>
<stringAttribute key="TCP_DISABLE_EXTENDED_MODE" value="true"/>
<booleanAttribute key="TCP_KILL_ON_EXIT" value="false"/>
<listAttribute key="TREE_NODE_PROPERTIES:debugger.view.ExpressionsView">
@@ -221,7 +224,7 @@
<booleanAttribute key="VFS_ENABLED" value="true"/>
<stringAttribute key="VFS_LOCAL_DIR" value="${workspace_loc}"/>
<stringAttribute key="VFS_REMOTE_MOUNT" value="/writeable"/>
<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
<stringAttribute key="breakpoints" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;breakpoints order=&quot;ALPHA&quot;&gt;&#10;&#9;&lt;breakpoint ignorecount=&quot;0&quot; threadenabled=&quot;no&quot; core_list=&quot;&quot; continue=&quot;no&quot; verboseBreakpoints=&quot;yes&quot; kind=&quot;SOURCEPOSITION&quot;&gt;&#10;&#9;&#9;&lt;master_location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x000000008000B64C&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;212&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;0&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL3:0x000000008000B64C&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;212&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&#9;&lt;location index=&quot;1&quot; enabled=&quot;true&quot; version=&quot;2&quot; address=&quot;EL1N:0x000000008000B64C&quot; debugFile=&quot;C:/Users/andrejm/work/git/AzureRTOS/threadx_andrejm_armv8a/ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/sample_threadx.c&quot; hostFile=&quot;C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\sample_threadx.c&quot; line=&quot;212&quot; function=&quot;thread_0_entry&quot;/&gt;&#10;&#9;&lt;/breakpoint&gt;&#10;&lt;/breakpoints&gt;&#10;"/>
<listAttribute key="com.arm.debug.views.common.AddressTracker.debugger.view.DisassemblyView.addresses">
<listEntry value=""/>
<listEntry value="&lt;Next Instruction&gt;"/>
@@ -363,7 +366,7 @@
<mapEntry key="6" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
<mapEntry key="7" value="NODE_TRANSFER_ELEMENT_COUNT,0;NODE_TRANSFER_ELEMENT_SIZE_IN_BYTES,4;NODE_TYPE,VALUE;FORMATTER,Unsigned Decimal"/>
</mapAttribute>
<stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;187&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;90&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;108&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;57&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;50&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;37&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;148&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;53&#9;-1&#9;true"/>
<stringAttribute key="debugger.view.ExpressionsView:DebugOutlineColumnState" value="OutlineConfig1&#9;8&#9;0&#9;true&#9;true&#9;255&#9;-1&#9;true&#9;1&#9;false&#9;true&#9;127&#9;-1&#9;true&#9;2&#9;true&#9;true&#9;159&#9;-1&#9;true&#9;3&#9;true&#9;true&#9;75&#9;-1&#9;true&#9;4&#9;true&#9;true&#9;65&#9;-1&#9;true&#9;5&#9;true&#9;true&#9;48&#9;-1&#9;true&#9;6&#9;true&#9;true&#9;241&#9;-1&#9;true&#9;7&#9;true&#9;true&#9;69&#9;-1&#9;true"/>
<stringAttribute key="debugger.view.MemoryView" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;&#10;&lt;page&gt;&#10;&#9;&lt;memoryView/&gt;&#10;&lt;/page&gt;&#10;"/>
<listAttribute key="debugger.view.MemoryView:current">
<listEntry value=""/>
@@ -386,7 +389,7 @@
<stringAttribute key="dtsl_options_file" value="default"/>
<stringAttribute key="dtsl_tracecapture_option" value="options.trace.traceCapture"/>
<booleanAttribute key="linuxOS" value="false"/>
<stringAttribute key="model_connection_address" value=""/>
<stringAttribute key="model_connection_address" value="127.0.0.1:7100"/>
<stringAttribute key="model_iris" value="1"/>
<stringAttribute key="model_params" value="-C bp.secure_memory=false -C cache_state_modelled=0"/>
<stringAttribute key="os_extension_id" value="com.arm.debug.os.threadx"/>
@@ -395,6 +398,7 @@
<mapAttribute key="scripts_view_script_links">
<mapEntry key="B:\support\broadcom\a53smp_el1_clean_mar25\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="B:\support\broadcom\tx58cortexa53arm\release\threadx\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_andrejm_armv8a\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\andrejm\work\git\AzureRTOS\threadx_other\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx\ports_smp\cortex_a35_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>
<mapEntry key="C:\Users\nisohack\Documents\work\x-ware_libs\threadx_github\ports\cortex_a5x_smp\ac6\example_build\sample_threadx\use_model_semihosting.ds" value=""/>

10
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/startup.S
View File

@@ -5,7 +5,7 @@
//
// Exits in EL1 AArch64
//
// Copyright (c) 2014-2017 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -19,7 +19,6 @@
.balign 4
.cfi_sections .debug_frame // put stack frame info into .debug_frame instead of .eh_frame
.global el1_vectors
.global el2_vectors
.global el3_vectors
@@ -31,6 +30,7 @@
.global SetSPISecurityAll
.global SetPrivateIntPriority
.global GetGICR
.global WakeupGICR
.global SyncAREinGICD
.global EnableGICD
@@ -533,7 +533,7 @@ el1_primary:
// VA->PA translation
//
bic x4, x4, #((1 << 21) - 1)
mov x1, #(TT_S1_ATTR_BLOCK | \
ldr x1, =(TT_S1_ATTR_BLOCK | \
(1 << TT_S1_ATTR_MATTR_LSB) | \
TT_S1_ATTR_NS | \
TT_S1_ATTR_AP_RW_PL1 | \
@@ -622,7 +622,7 @@ nol2setup:
// translation
//
bic x4, x4, #((1 << 21) - 1) // start address mod 2MB
mov x1, #(TT_S1_ATTR_BLOCK | \
ldr x1, =(TT_S1_ATTR_BLOCK | \
(2 << TT_S1_ATTR_MATTR_LSB) | \
TT_S1_ATTR_NS | \
TT_S1_ATTR_AP_RW_PL1 | \
@@ -657,7 +657,7 @@ nol2setup:
// translation
//
bic x4, x4, #((1 << 21) - 1) // start address mod 2MB
mov x1, #(TT_S1_ATTR_BLOCK | \
ldr x1, =(TT_S1_ATTR_BLOCK | \
(2 << TT_S1_ATTR_MATTR_LSB) | \
TT_S1_ATTR_NS | \
TT_S1_ATTR_AP_RW_PL1 | \

18
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/timer_interrupts.c
View File

@@ -2,10 +2,10 @@
/* Timer and interrupts */
/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */
/* Use, modification and redistribution of this file is subject to your */
/* possession of a valid DS-5 end user licence agreement and your compliance */
/* with all applicable terms and conditions of such licence agreement. */
/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
/* Use, modification and redistribution of this file is subject to your possession of a */
/* valid End User License Agreement for the Arm Product of which these examples are part of */
/* and your compliance with all applicable terms and conditions of such licence agreement. */
#include <stdio.h>
@@ -112,14 +112,14 @@ void fiqHandler(void)
unsigned int aliased = 0;
ID = getICC_IAR0(); // readIntAck();
printf("fiqHandler() - Read %d from IAR0\n", ID);
//printf("fiqHandler() - Read %d from IAR0\n", ID);
// Check for reserved IDs
if ((1020 <= ID) && (ID <= 1023))
{
printf("fiqHandler() - Reserved INTID %d\n\n", ID);
//printf("fiqHandler() - Reserved INTID %d\n\n", ID);
ID = getICC_IAR1(); // readAliasedIntAck();
printf("fiqHandler() - Read %d from AIAR\n", ID);
//printf("fiqHandler() - Read %d from AIAR\n", ID);
aliased = 1;
// If still spurious then simply return
@@ -131,13 +131,13 @@ void fiqHandler(void)
{
case 34:
// Dual-Timer 0 (SP804)
printf("fiqHandler() - External timer interrupt\n\n");
//printf("fiqHandler() - External timer interrupt\n\n");
clearTimerIrq();
break;
default:
// Unexpected ID value
printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
//printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
break;
}

20
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.S
View File

@@ -1,7 +1,7 @@
// ------------------------------------------------------------
// Armv8-A AArch64 - Common helper functions
//
// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -17,6 +17,7 @@
.global InvalidateUDCaches
.global GetMIDR
.global GetMPIDR
.global GetAffinity
.global GetCPUID
// ------------------------------------------------------------
@@ -138,12 +139,25 @@ GetMPIDR:
.cfi_endproc
.type GetAffinity, "function"
.cfi_startproc
GetAffinity:
mrs x0, MPIDR_EL1
ubfx x1, x0, #32, #8
bfi w0, w1, #24, #8
ret
.cfi_endproc
.type GetCPUID, "function"
.cfi_startproc
GetCPUID:
mrs x0, MIDR_EL1
ubfx x0, x0, #4, #12 // extract PartNum
cmp x0, #0xD0D // Cortex-A77
b.eq DynamIQ
cmp x0, #0xD0B // Cortex-A76
b.eq DynamIQ
cmp x0, #0xD0A // Cortex-A75
@@ -158,6 +172,8 @@ DynamIQ:
Others:
mrs x0, MPIDR_EL1
ubfx x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
ubfx x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
ubfx x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
add x0, x1, x2, LSL #2
ret
.cfi_endproc

103
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_aarch64.h Normal file
View File

@@ -0,0 +1,103 @@
/*
*
* Armv8-A AArch64 common helper functions
*
* Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef V8_AARCH64_H
#define V8_AARCH64_H
/*
* Parameters for data barriers
*/
#define OSHLD 1
#define OSHST 2
#define OSH 3
#define NSHLD 5
#define NSHST 6
#define NSH 7
#define ISHLD 9
#define ISHST 10
#define ISH 11
#define LD 13
#define ST 14
#define SY 15
/**********************************************************************/
/*
* function prototypes
*/
/*
* void InvalidateUDCaches(void)
* invalidates all Unified and Data Caches
*
* Inputs
* <none>
*
* Returns
* <nothing>
*
* Side Effects
* guarantees that all levels of cache will be invalidated before
* returning to caller
*/
void InvalidateUDCaches(void);
/*
* unsigned long long EnableCachesEL1(void)
* enables I- and D- caches at EL1
*
* Inputs
* <none>
*
* Returns
* New value of SCTLR_EL1
*
* Side Effects
* context will be synchronised before returning to caller
*/
unsigned long long EnableCachesEL1(void);
/*
* unsigned long long GetMIDR(void)
* returns the contents of MIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MIDR_EL0
*/
unsigned long long GetMIDR(void);
/*
* unsigned long long GetMPIDR(void)
* returns the contents of MPIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MPIDR_EL0
*/
unsigned long long GetMPIDR(void);
/*
* unsigned int GetCPUID(void)
* returns the Aff0 field of MPIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MPIDR_EL0[7:0]
*/
unsigned int GetCPUID(void);
#endif

12
ports_smp/cortex_a35_smp/ac6/example_build/sample_threadx/v8_mmu.h
View File

@@ -1,7 +1,7 @@
//
// Defines for v8 Memory Model
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -90,10 +90,20 @@
#define TT_S1_ATTR_AF (1 << 10)
#define TT_S1_ATTR_nG (1 << 11)
// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
// and bits[47:16] are bits[47:16] of the output address for a page of memory
#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
#define TT_S1_ATTR_CONTIG (1 << 52)
#define TT_S1_ATTR_PXN (1 << 53)
#define TT_S1_ATTR_UXN (1 << 54)
// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits
// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
#define TT_S1_MAIR_DEV_nGnRE 0b00000100
#define TT_S1_MAIR_DEV_nGRE 0b00001000

36
ports_smp/cortex_a35_smp/ac6/example_build/tx/.cproject
View File

@@ -7,7 +7,19 @@
<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944" moduleId="org.eclipse.cdt.core.settings" name="Debug">
<externalSettings/>
<externalSettings>
<externalSetting>
<entry flags="VALUE_WORKSPACE_PATH" kind="includePath" name="/tx"/>
<entry flags="VALUE_WORKSPACE_PATH" kind="libraryPath" name="/tx/Debug"/>
<entry flags="RESOLVED" kind="libraryFile" name="tx" srcPrefixMapping="" srcRootPath=""/>
</externalSetting>
</externalSettings>
<extensions>
@@ -105,9 +117,29 @@
</folderInfo>
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.214318543" name="tx_thread_timeout.c" rcbsApplicability="disable" resourcePath="src_generic/tx_thread_timeout.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1899536638">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1899536638" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1006773355" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
</fileInfo>
<fileInfo id="com.arm.eclipse.build.config.v6.lib.debug.base.1470528944.1145515026" name="tx_misra.c" rcbsApplicability="disable" resourcePath="src_generic/tx_misra.c" toolsToInvoke="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128">
<tool id="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428.1242981128" name="Arm C Compiler 6" superClass="com.arm.tool.c.compiler.v6.base.var.arm_compiler_6-6.2072709428">
<inputType id="com.arm.tool.c.compiler.v6.base.input.1275109624" superClass="com.arm.tool.c.compiler.v6.base.input"/>
</tool>
</fileInfo>
<sourceEntries>
<entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>

16
ports_smp/cortex_a35_smp/ac6/inc/tx_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* tx_port.h ARMv8-A-SMP */
/* 6.1.10 */
/* */
/* AUTHOR */
/* */
@@ -48,12 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* 10-15-2021 William E. Lamie Modified comment(s), added */
/* symbol ULONG64_DEFINED, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
@@ -408,8 +405,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define VFP extension for the Cortex-A35. Each is assumed to be called in the context of the executing
thread. */
/* Define FP extension for ARMv8. Each is assumed to be called in the context of the executing thread. */
#ifndef TX_SOURCE_CODE
#define tx_thread_fp_enable _tx_thread_fp_enable
@@ -424,7 +420,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/AC6 Version 6.1.9 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *";
#else
extern CHAR _tx_version_id[];
#endif

8
ports_smp/cortex_a35_smp/ac6/src/tx_initialize_low_level.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_initialize_low_level ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -62,8 +62,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)

10
ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_restore.S
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,9 +64,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -79,7 +79,7 @@ _tx_thread_context_restore:
MSR DAIFSet, 0x3 // Lockout interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */

12
ports_smp/cortex_a35_smp/ac6/src/tx_thread_context_save.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_context_save ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,9 +60,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)
@@ -135,7 +135,7 @@ _tx_thread_context_save:
#endif
STP x0, x1, [sp, #-16]! // Save SPSR, ELR
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */
@@ -238,7 +238,7 @@ __tx_thread_idle_system_save:
/* Not much to do here, just adjust the stack pointer, and return to IRQ
processing. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */

8
ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_disable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_disable Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_fp_disable ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,8 +64,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_disable(VOID)

8
ports_smp/cortex_a35_smp/ac6/src/tx_thread_fp_enable.c
View File

@@ -32,8 +32,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_enable Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_fp_enable ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,8 +63,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_enable(VOID)

9
ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_control.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_interrupt_control ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -79,4 +79,3 @@ _tx_thread_interrupt_control:
MOV x0, x1 // Setup return value
RET // Return to caller
// }

8
ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_disable.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_interrupt_disable ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,8 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(void)

8
ports_smp/cortex_a35_smp/ac6/src/tx_thread_interrupt_restore.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_interrupt_restore ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_restore(UINT old_posture)

10
ports_smp/cortex_a35_smp/ac6/src/tx_thread_schedule.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_schedule ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -62,9 +62,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -205,7 +205,7 @@ _execute_pointer_did_not_change:
MOV sp, x4 //
STR w3, [x2, x20, LSL #2] // Setup time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread entry function to indicate the thread is executing. */

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_get.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,9 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_get

11
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_core_preempt.S
View File

@@ -21,14 +21,17 @@
/**************************************************************************/
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -62,9 +65,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_preempt

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_state_get.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,9 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_state_get

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_current_thread_get.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,9 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_thread_get

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_initialize_wait.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,9 +60,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_initialize_wait

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_low_level_initialize.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_low_level_initialize

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_protect.S
View File

@@ -32,7 +32,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,10 +64,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* improved SMP code, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_protect

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_time_get.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_time_get

6
ports_smp/cortex_a35_smp/ac6/src/tx_thread_smp_unprotect.S
View File

@@ -28,7 +28,7 @@
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,9 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect

8
ports_smp/cortex_a35_smp/ac6/src/tx_thread_stack_build.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_stack_build ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,8 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

10
ports_smp/cortex_a35_smp/ac6/src/tx_thread_system_return.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_thread_system_return ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,9 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)
@@ -117,7 +117,7 @@ _skip_fp_save:
MOV x1, #0 // Clear x1
STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */

166
ports_smp/cortex_a35_smp/ac6/src/tx_thread_timeout.c
View File

@@ -1,166 +0,0 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
/* Include necessary system files. */
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_timeout Cortex-A35-SMP */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function handles thread timeout processing. Timeouts occur in */
/* two flavors, namely the thread sleep timeout and all other service */
/* call timeouts. Thread sleep timeouts are processed locally, while */
/* the others are processed by the appropriate suspension clean-up */
/* service. */
/* */
/* INPUT */
/* */
/* timeout_input Contains the thread pointer */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* Suspension Cleanup Functions */
/* _tx_thread_system_resume Resume thread */
/* _tx_thread_system_ni_resume Non-interruptable resume thread */
/* */
/* CALLED BY */
/* */
/* _tx_timer_expiration_process Timer expiration function */
/* _tx_timer_thread_entry Timer thread function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_timeout(ULONG timeout_input)
{
TX_INTERRUPT_SAVE_AREA
TX_THREAD *thread_ptr;
VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
ULONG suspension_sequence;
/* Pickup the thread pointer. */
TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr)
/* Disable interrupts. */
TX_DISABLE
/* Determine how the thread is currently suspended. */
if (thread_ptr -> tx_thread_state == TX_SLEEP)
{
#ifdef TX_NOT_INTERRUPTABLE
/* Resume the thread! */
_tx_thread_system_ni_resume(thread_ptr);
/* Restore interrupts. */
TX_RESTORE
#else
/* Increment the disable preemption flag. */
_tx_thread_preempt_disable++;
/* Restore interrupts. */
TX_RESTORE
/* Lift the suspension on the sleeping thread. */
_tx_thread_system_resume(thread_ptr);
#endif
}
else
{
/* Process all other suspension timeouts. */
#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO
/* Increment the total number of thread timeouts. */
_tx_thread_performance_timeout_count++;
/* Increment the number of timeouts for this thread. */
thread_ptr -> tx_thread_performance_timeout_count++;
#endif
/* Pickup the cleanup routine address. */
suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup;
#ifndef TX_NOT_INTERRUPTABLE
/* Pickup the suspension sequence number that is used later to verify that the
cleanup is still necessary. */
suspension_sequence = thread_ptr -> tx_thread_suspension_sequence;
#else
/* When not interruptable is selected, the suspension sequence is not used - just set to 0. */
suspension_sequence = ((ULONG) 0);
#endif
#ifndef TX_NOT_INTERRUPTABLE
/* Restore interrupts. */
TX_RESTORE
#endif
/* Call any cleanup routines. */
if (suspend_cleanup != TX_NULL)
{
/* Yes, there is a function to call. */
(suspend_cleanup)(thread_ptr, suspension_sequence);
}
#ifdef TX_NOT_INTERRUPTABLE
/* Restore interrupts. */
TX_RESTORE
#endif
}
}

4
ports_smp/cortex_a35_smp/ac6/src/tx_timer_interrupt.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-A35-SMP/AC6 */
/* 6.1.9 */
/* _tx_timer_interrupt ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */

21
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/GICv3_gicr.c
View File

@@ -1,7 +1,7 @@
/*
* GICv3_gicr.c - generic driver code for GICv3 redistributor
*
* Copyright (c) 2014-2018 Arm Limited (or its affiliates). All rights reserved.
* Copyright (c) 2014-2019 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
@@ -129,6 +129,25 @@ static inline GICv3_redistributor_SGI *const getgicrSGI(uint32_t gicr)
/**********************************************************************/
// This function walks a block of RDs to find one with the matching affinity
uint32_t GetGICR(uint32_t affinity)
{
GICv3_redistributor_RD* gicr;
uint32_t index = 0;
do
{
gicr = getgicrRD(index);
if (gicr->GICR_TYPER[1] == affinity)
return index;
index++;
}
while((gicr->GICR_TYPER[0] & (1<<4)) == 0); // Keep looking until GICR_TYPER.Last reports no more RDs in block
return 0xFFFFFFFF; // return -1 to signal not RD found
}
void WakeupGICR(uint32_t gicr)
{
GICv3_redistributor_RD *const gicrRD = getgicrRD(gicr);

49
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.S
View File

@@ -1,7 +1,8 @@
//
// Armv8-A AArch64 - Basic Mutex Example
// Includes the option (USE_LSE_ATOMIC) to use Large System Extension (LSE) atomics introduced in Armv8.1-A
//
// Copyright (c) 2012-2017 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -43,6 +44,7 @@ _mutex_initialize:
ret
.cfi_endproc
#if !defined(USE_LSE_ATOMIC)
.type _mutex_acquire, "function"
.cfi_startproc
@@ -84,3 +86,48 @@ _mutex_release:
stlr w1, [x0]
ret
.cfi_endproc
#else // LSE version
.type _mutex_acquire, "function"
.cfi_startproc
_mutex_acquire:
// This uses a "ticket lock". The lock is stored as a 32-bit value:
// - the upper 16-bits record the thread's ticket number ("take a ticket")
// - the lower 16-bits record the ticket being served ("now serving")
// atomically load then increment the thread's ticket number ("take a ticket")
mov w3, #(1 << 16)
ldadda w3, w1, [x0]
// is the ticket now being served?
eor w2, w1, w1, ror #16
cbz w2, loop_exit
// no, so wait for the ticket to be served
// send a local event to avoid missing an unlock before the exclusive load
sevl
loop:
wfe
ldaxrh w3, [x0]
eor w2, w3, w1, lsr #16
cbnz w2, loop
//
// OK, we have the mutex, our work is done here
//
loop_exit:
ret
.cfi_endproc
.type _mutex_release, "function"
.cfi_startproc
_mutex_release:
mov w1, #1
staddlh w1, [x0]
ret
.cfi_endproc
#endif

66
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/MP_Mutexes.h Normal file
View File

@@ -0,0 +1,66 @@
/*
* Armv8-A AArch64 - Basic Mutex Example
*
* Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef MP_MUTEX_H
#define MP_MUTEX_H
/*
* The Arm C library calls-out to these functions to manage multithreading.
* They can also be called by user application code.
*
* Mutex type is specified by the Arm C library
*
* Declare function prototypes for libc mutex routines
*/
typedef signed int *mutex;
/*
* int _mutex_initialize(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* 0 - application is non-threaded
* 1 - application is threaded
* The C library uses the return result to indicate whether it is being used in a multithreaded environment.
*/
int _mutex_initialize(mutex *m);
/*
* void _mutex_acquire(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* <nothing>
*
* Side Effects
* Routine does not return until the mutex has been claimed. A load-acquire
* is used to guarantee that the mutex claim is properly ordered with
* respect to any accesses to the resource protected by the mutex
*/
void _mutex_acquire(mutex *m);
/*
* void _mutex_release(mutex *m)
*
* Inputs
* mutex *m - pointer to the 32-bit word associated with the mutex
*
* Returns
* <nothing>
*
* Side Effects
* A store-release is used to guarantee that the mutex release is properly
* ordered with respect any accesses to the resource protected by the mutex
*/
void _mutex_release(mutex *m);
#endif

22
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/sample_threadx.c
View File

@@ -3,19 +3,22 @@
byte pool, and block pool. */
#include "tx_api.h"
#include <stddef.h>
extern void init_timer(void); /* in timer_interrupts.c */
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 0x20000
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
#define DEMO_STACK_SIZE 1024
#define DEMO_BYTE_POOL_SIZE 9120
#define DEMO_BLOCK_POOL_SIZE 100
#define DEMO_QUEUE_SIZE 100
/* Define a memory area to create a byte pool in. */
/* Define byte pool memory. */
UCHAR byte_pool_memory[DEMO_BYTE_POOL_SIZE];
UCHAR memory_area[DEMO_BYTE_POOL_SIZE] __attribute__((aligned (8)));
/* Define the ThreadX object control blocks... */
@@ -68,6 +71,8 @@ UCHAR event_buffer[65536];
#endif
/* Define main entry point. */
int main(void)
{
@@ -95,7 +100,7 @@ CHAR *pointer = TX_NULL;
#endif
/* Create a byte memory pool from which to allocate the thread stacks. */
tx_byte_pool_create(&byte_pool_0, "byte pool 0", memory_area, DEMO_BYTE_POOL_SIZE);
tx_byte_pool_create(&byte_pool_0, "byte pool 0", byte_pool_memory, DEMO_BYTE_POOL_SIZE);
/* Allocate the stack for thread 0. */
tx_byte_allocate(&byte_pool_0, (VOID **) &pointer, DEMO_STACK_SIZE, TX_NO_WAIT);
@@ -386,4 +391,3 @@ UINT status;
break;
}
}

18
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/timer_interrupts.c
View File

@@ -2,10 +2,10 @@
/* Timer and interrupts */
/* Copyright (c) 2016 Arm Limited (or its affiliates). All rights reserved. */
/* Use, modification and redistribution of this file is subject to your */
/* possession of a valid DS-5 end user licence agreement and your compliance */
/* with all applicable terms and conditions of such licence agreement. */
/* Copyright (c) 2016-2018 Arm Limited (or its affiliates). All rights reserved. */
/* Use, modification and redistribution of this file is subject to your possession of a */
/* valid End User License Agreement for the Arm Product of which these examples are part of */
/* and your compliance with all applicable terms and conditions of such licence agreement. */
#include <stdio.h>
@@ -112,14 +112,14 @@ void fiqHandler(void)
unsigned int aliased = 0;
ID = getICC_IAR0(); // readIntAck();
printf("fiqHandler() - Read %d from IAR0\n", ID);
//printf("fiqHandler() - Read %d from IAR0\n", ID);
// Check for reserved IDs
if ((1020 <= ID) && (ID <= 1023))
{
printf("fiqHandler() - Reserved INTID %d\n\n", ID);
//printf("fiqHandler() - Reserved INTID %d\n\n", ID);
ID = getICC_IAR1(); // readAliasedIntAck();
printf("fiqHandler() - Read %d from AIAR\n", ID);
//printf("fiqHandler() - Read %d from AIAR\n", ID);
aliased = 1;
// If still spurious then simply return
@@ -131,13 +131,13 @@ void fiqHandler(void)
{
case 34:
// Dual-Timer 0 (SP804)
printf("fiqHandler() - External timer interrupt\n\n");
//printf("fiqHandler() - External timer interrupt\n\n");
clearTimerIrq();
break;
default:
// Unexpected ID value
printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
//printf("fiqHandler() - Unexpected INTID %d\n\n", ID);
break;
}

20
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.S
View File

@@ -1,7 +1,7 @@
// ------------------------------------------------------------
// Armv8-A AArch64 - Common helper functions
//
// Copyright (c) 2012-2018 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -17,6 +17,7 @@
.global InvalidateUDCaches
.global GetMIDR
.global GetMPIDR
.global GetAffinity
.global GetCPUID
// ------------------------------------------------------------
@@ -138,12 +139,25 @@ GetMPIDR:
.cfi_endproc
.type GetAffinity, "function"
.cfi_startproc
GetAffinity:
mrs x0, MPIDR_EL1
ubfx x1, x0, #32, #8
bfi w0, w1, #24, #8
ret
.cfi_endproc
.type GetCPUID, "function"
.cfi_startproc
GetCPUID:
mrs x0, MIDR_EL1
ubfx x0, x0, #4, #12 // extract PartNum
cmp x0, #0xD0D // Cortex-A77
b.eq DynamIQ
cmp x0, #0xD0B // Cortex-A76
b.eq DynamIQ
cmp x0, #0xD0A // Cortex-A75
@@ -158,6 +172,8 @@ DynamIQ:
Others:
mrs x0, MPIDR_EL1
ubfx x0, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
ubfx x1, x0, #MPIDR_EL1_AFF0_LSB, #MPIDR_EL1_AFF_WIDTH
ubfx x2, x0, #MPIDR_EL1_AFF1_LSB, #MPIDR_EL1_AFF_WIDTH
add x0, x1, x2, LSL #2
ret
.cfi_endproc

103
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_aarch64.h Normal file
View File

@@ -0,0 +1,103 @@
/*
*
* Armv8-A AArch64 common helper functions
*
* Copyright (c) 2012-2014 Arm Limited (or its affiliates). All rights reserved.
* Use, modification and redistribution of this file is subject to your possession of a
* valid End User License Agreement for the Arm Product of which these examples are part of
* and your compliance with all applicable terms and conditions of such licence agreement.
*/
#ifndef V8_AARCH64_H
#define V8_AARCH64_H
/*
* Parameters for data barriers
*/
#define OSHLD 1
#define OSHST 2
#define OSH 3
#define NSHLD 5
#define NSHST 6
#define NSH 7
#define ISHLD 9
#define ISHST 10
#define ISH 11
#define LD 13
#define ST 14
#define SY 15
/**********************************************************************/
/*
* function prototypes
*/
/*
* void InvalidateUDCaches(void)
* invalidates all Unified and Data Caches
*
* Inputs
* <none>
*
* Returns
* <nothing>
*
* Side Effects
* guarantees that all levels of cache will be invalidated before
* returning to caller
*/
void InvalidateUDCaches(void);
/*
* unsigned long long EnableCachesEL1(void)
* enables I- and D- caches at EL1
*
* Inputs
* <none>
*
* Returns
* New value of SCTLR_EL1
*
* Side Effects
* context will be synchronised before returning to caller
*/
unsigned long long EnableCachesEL1(void);
/*
* unsigned long long GetMIDR(void)
* returns the contents of MIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MIDR_EL0
*/
unsigned long long GetMIDR(void);
/*
* unsigned long long GetMPIDR(void)
* returns the contents of MPIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MPIDR_EL0
*/
unsigned long long GetMPIDR(void);
/*
* unsigned int GetCPUID(void)
* returns the Aff0 field of MPIDR_EL0
*
* Inputs
* <none>
*
* Returns
* MPIDR_EL0[7:0]
*/
unsigned int GetCPUID(void);
#endif

12
ports_smp/cortex_a35_smp/gnu/example_build/sample_threadx/v8_mmu.h
View File

@@ -1,7 +1,7 @@
//
// Defines for v8 Memory Model
//
// Copyright (c) 2012-2016 Arm Limited (or its affiliates). All rights reserved.
// Copyright (c) 2012-2019 Arm Limited (or its affiliates). All rights reserved.
// Use, modification and redistribution of this file is subject to your possession of a
// valid End User License Agreement for the Arm Product of which these examples are part of
// and your compliance with all applicable terms and conditions of such licence agreement.
@@ -90,10 +90,20 @@
#define TT_S1_ATTR_AF (1 << 10)
#define TT_S1_ATTR_nG (1 << 11)
// OA bits [15:12] - If Armv8.2-LPA is implemented, bits[15:12] are bits[51:48]
// and bits[47:16] are bits[47:16] of the output address for a page of memory
#define TT_S1_ATTR_nT (1 << 16) // Present if Armv8.4-TTRem is implemented, otherwise RES0
#define TT_S1_ATTR_DBM (1 << 51) // Present if Armv8.1-TTHM is implemented, otherwise RES0
#define TT_S1_ATTR_CONTIG (1 << 52)
#define TT_S1_ATTR_PXN (1 << 53)
#define TT_S1_ATTR_UXN (1 << 54)
// PBHA bits[62:59] - If Armv8.2-TTPBHA is implemented, hardware can use these bits
// for IMPLEMENTATIONDEFINED purposes, otherwise IGNORED
#define TT_S1_MAIR_DEV_nGnRnE 0b00000000
#define TT_S1_MAIR_DEV_nGnRE 0b00000100
#define TT_S1_MAIR_DEV_nGRE 0b00001000

2
ports_smp/cortex_a35_smp/gnu/example_build/tx/.cproject
View File

@@ -131,7 +131,7 @@
<sourceEntries>
<entry excluding="src_generic/tx_misra.c|src_generic/tx_thread_timeout.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>

13
ports_smp/cortex_a35_smp/gnu/inc/tx_port.h
View File

@@ -25,8 +25,8 @@
/* */
/* PORT SPECIFIC C INFORMATION RELEASE */
/* */
/* tx_port.h Cortex-A35-SMP/GNU */
/* 6.1.6 */
/* tx_port.h ARMv8-A-SMP */
/* 6.1.10 */
/* */
/* AUTHOR */
/* */
@@ -48,9 +48,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 04-02-2021 Bhupendra Naphade Modified comment(s),updated */
/* 01-31-2022 Bhupendra Naphade Modified comment(s),updated */
/* macro definition, */
/* resulting in version 6.1.6 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
@@ -405,8 +405,7 @@ typedef struct TX_THREAD_SMP_PROTECT_STRUCT
#define TX_SEMAPHORE_DISABLE TX_DISABLE
/* Define VFP extension for the Cortex-A35. Each is assumed to be called in the context of the executing
thread. */
/* Define FP extension for ARMv8. Each is assumed to be called in the context of the executing thread. */
#ifndef TX_SOURCE_CODE
#define tx_thread_fp_enable _tx_thread_fp_enable
@@ -421,7 +420,7 @@ VOID tx_thread_fp_disable(VOID);
#ifdef TX_THREAD_INIT
CHAR _tx_version_id[] =
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX Cortex-A35-SMP/GNU Version 6.1.9 *";
"Copyright (c) Microsoft Corporation. All rights reserved. * ThreadX ARMv8-A-SMP Version 6.1.10 *";
#else
extern CHAR _tx_version_id[];
#endif

8
ports_smp/cortex_a35_smp/gnu/src/tx_initialize_low_level.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_initialize_low_level Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_initialize_low_level ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -62,8 +62,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_initialize_low_level(VOID)

10
ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_restore.S
View File

@@ -30,8 +30,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_restore Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_context_restore ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,9 +64,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_restore(VOID)
@@ -79,7 +79,7 @@ _tx_thread_context_restore:
MSR DAIFSet, 0x3 // Lockout interrupts
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR exit function to indicate an ISR is complete. */

12
ports_smp/cortex_a35_smp/gnu/src/tx_thread_context_save.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_context_save Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_context_save ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,9 +60,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_context_save(VOID)
@@ -135,7 +135,7 @@ _tx_thread_context_save:
#endif
STP x0, x1, [sp, #-16]! // Save SPSR, ELR
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */
@@ -238,7 +238,7 @@ __tx_thread_idle_system_save:
/* Not much to do here, just adjust the stack pointer, and return to IRQ
processing. */
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the ISR enter function to indicate an ISR is executing. */

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_disable.c
View File

@@ -33,8 +33,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_disable Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_fp_disable ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,8 +64,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_disable(VOID)

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_fp_enable.c
View File

@@ -32,8 +32,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_fp_enable Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_fp_enable ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,8 +63,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
VOID _tx_thread_fp_enable(VOID)

9
ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_control.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_control Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_interrupt_control ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_control(UINT new_posture)
@@ -79,4 +79,3 @@ _tx_thread_interrupt_control:
MOV x0, x1 // Setup return value
RET // Return to caller
// }

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_disable.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_disable Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_interrupt_disable ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,8 +58,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_disable(void)

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_interrupt_restore.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_interrupt_restore Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_interrupt_restore ARMv8-A */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// UINT _tx_thread_interrupt_restore(UINT old_posture)

10
ports_smp/cortex_a35_smp/gnu/src/tx_thread_schedule.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_schedule Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_schedule ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -62,9 +62,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_schedule(VOID)
@@ -205,7 +205,7 @@ _execute_pointer_did_not_change:
MOV sp, x4 //
STR w3, [x2, x20, LSL #2] // Setup time-slice
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread entry function to indicate the thread is executing. */

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_get.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_core_get Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,9 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_get

9
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_core_preempt.S
View File

@@ -23,14 +23,15 @@
#define ICC_SGI1R_EL1 S3_0_C12_C11_5
.text
.align 3
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_core_preempt Cortex-A35-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,9 +65,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_core_preempt

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_state_get.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_current_state_get Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,9 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_state_get

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_current_thread_get.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_current_thread_get Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -58,9 +58,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_current_thread_get

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_initialize_wait.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_initialize_wait Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -60,9 +60,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_initialize_wait

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_low_level_initialize.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_low_level_initialize Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_low_level_initialize

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_protect.S
View File

@@ -31,8 +31,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_protect Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_protect Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -64,10 +64,10 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* improved SMP code, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_protect

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_time_get.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_time_get Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_time_get Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -59,8 +59,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_time_get

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_smp_unprotect.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_smp_unprotect Cortex-A35-SMP/AC6 */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,9 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
.global _tx_thread_smp_unprotect

8
ports_smp/cortex_a35_smp/gnu/src/tx_thread_stack_build.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_stack_build Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_stack_build ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,8 +61,8 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))

10
ports_smp/cortex_a35_smp/gnu/src/tx_thread_system_return.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_system_return Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_thread_system_return ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -61,9 +61,9 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* 01-31-2022 Andres Mlinar Updated comments, */
/* added ARMv8.2-A support, */
/* resulting in version 6.1.9 */
/* resulting in version 6.1.10 */
/* */
/**************************************************************************/
// VOID _tx_thread_system_return(VOID)
@@ -117,7 +117,7 @@ _skip_fp_save:
MOV x1, #0 // Clear x1
STP x0, x1, [sp, #-16]! // Save DAIF and clear value for ELR_EK1
#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
/* Call the thread exit function to indicate the thread is no longer executing. */

166
ports_smp/cortex_a35_smp/gnu/src/tx_thread_timeout.c
View File

@@ -1,166 +0,0 @@
/**************************************************************************/
/* */
/* Copyright (c) Microsoft Corporation. All rights reserved. */
/* */
/* This software is licensed under the Microsoft Software License */
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
/* and in the root directory of this software. */
/* */
/**************************************************************************/
/**************************************************************************/
/**************************************************************************/
/** */
/** ThreadX Component */
/** */
/** Thread */
/** */
/**************************************************************************/
/**************************************************************************/
#define TX_SOURCE_CODE
/* Include necessary system files. */
#include "tx_api.h"
#include "tx_thread.h"
#include "tx_timer.h"
/**************************************************************************/
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_thread_timeout Cortex-A35-SMP */
/* 6.1.9 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
/* */
/* DESCRIPTION */
/* */
/* This function handles thread timeout processing. Timeouts occur in */
/* two flavors, namely the thread sleep timeout and all other service */
/* call timeouts. Thread sleep timeouts are processed locally, while */
/* the others are processed by the appropriate suspension clean-up */
/* service. */
/* */
/* INPUT */
/* */
/* timeout_input Contains the thread pointer */
/* */
/* OUTPUT */
/* */
/* None */
/* */
/* CALLS */
/* */
/* Suspension Cleanup Functions */
/* _tx_thread_system_resume Resume thread */
/* _tx_thread_system_ni_resume Non-interruptable resume thread */
/* */
/* CALLED BY */
/* */
/* _tx_timer_expiration_process Timer expiration function */
/* _tx_timer_thread_entry Timer thread function */
/* */
/* RELEASE HISTORY */
/* */
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Andres Mlinar Updated comments, */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
VOID _tx_thread_timeout(ULONG timeout_input)
{
TX_INTERRUPT_SAVE_AREA
TX_THREAD *thread_ptr;
VOID (*suspend_cleanup)(struct TX_THREAD_STRUCT *suspend_thread_ptr, ULONG suspension_sequence);
ULONG suspension_sequence;
/* Pickup the thread pointer. */
TX_THREAD_TIMEOUT_POINTER_SETUP(thread_ptr)
/* Disable interrupts. */
TX_DISABLE
/* Determine how the thread is currently suspended. */
if (thread_ptr -> tx_thread_state == TX_SLEEP)
{
#ifdef TX_NOT_INTERRUPTABLE
/* Resume the thread! */
_tx_thread_system_ni_resume(thread_ptr);
/* Restore interrupts. */
TX_RESTORE
#else
/* Increment the disable preemption flag. */
_tx_thread_preempt_disable++;
/* Restore interrupts. */
TX_RESTORE
/* Lift the suspension on the sleeping thread. */
_tx_thread_system_resume(thread_ptr);
#endif
}
else
{
/* Process all other suspension timeouts. */
#ifdef TX_THREAD_ENABLE_PERFORMANCE_INFO
/* Increment the total number of thread timeouts. */
_tx_thread_performance_timeout_count++;
/* Increment the number of timeouts for this thread. */
thread_ptr -> tx_thread_performance_timeout_count++;
#endif
/* Pickup the cleanup routine address. */
suspend_cleanup = thread_ptr -> tx_thread_suspend_cleanup;
#ifndef TX_NOT_INTERRUPTABLE
/* Pickup the suspension sequence number that is used later to verify that the
cleanup is still necessary. */
suspension_sequence = thread_ptr -> tx_thread_suspension_sequence;
#else
/* When not interruptable is selected, the suspension sequence is not used - just set to 0. */
suspension_sequence = ((ULONG) 0);
#endif
#ifndef TX_NOT_INTERRUPTABLE
/* Restore interrupts. */
TX_RESTORE
#endif
/* Call any cleanup routines. */
if (suspend_cleanup != TX_NULL)
{
/* Yes, there is a function to call. */
(suspend_cleanup)(thread_ptr, suspension_sequence);
}
#ifdef TX_NOT_INTERRUPTABLE
/* Restore interrupts. */
TX_RESTORE
#endif
}
}

6
ports_smp/cortex_a35_smp/gnu/src/tx_timer_interrupt.S
View File

@@ -27,8 +27,8 @@
/* */
/* FUNCTION RELEASE */
/* */
/* _tx_timer_interrupt Cortex-A35-SMP/GCC */
/* 6.1.9 */
/* _tx_timer_interrupt ARMv8-A-SMP */
/* 6.1.10 */
/* AUTHOR */
/* */
/* William E. Lamie, Microsoft Corporation */
@@ -63,8 +63,6 @@
/* DATE NAME DESCRIPTION */
/* */
/* 09-30-2020 William E. Lamie Initial Version 6.1 */
/* 10-15-2021 Yuxin Zhou Modified comment(s), */
/* resulting in version 6.1.9 */
/* */
/**************************************************************************/
// VOID _tx_timer_interrupt(VOID)