260 lines
11 KiB
Plaintext
260 lines
11 KiB
Plaintext
;/***************************************************************************
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; * Copyright (c) 2024 Microsoft Corporation
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; *
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; * This program and the accompanying materials are made available under the
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; * terms of the MIT License which is available at
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; * https://opensource.org/licenses/MIT.
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; *
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; * SPDX-License-Identifier: MIT
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; **************************************************************************/
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;
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;
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;/**************************************************************************/
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;/**************************************************************************/
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;/** */
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;/** ThreadX Component */
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;/** */
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;/** Thread */
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;/** */
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;/**************************************************************************/
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;/**************************************************************************/
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;
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;
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;#define TX_SOURCE_CODE
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;
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;
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;/* Include necessary system files. */
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;
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;#include "tx_api.h"
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;#include "tx_thread.h"
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;#include "tx_timer.h"
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;
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;
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.GLB __tx_thread_execute_ptr
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.GLB __tx_thread_current_ptr
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.GLB __tx_timer_time_slice
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.IF TX_LOW_POWER==1
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.GLB _tx_low_power_enter
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.GLB _tx_low_power_exit
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.GLB __tx_thread_preempt_disable
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.ENDIF
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;
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.SECTION P,CODE
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;/**************************************************************************/
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;/* */
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;/* FUNCTION RELEASE */
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;/* */
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;/* _tx_thread_schedule RXv3/CCRX */
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;/* 6.1.11 */
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;/* AUTHOR */
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;/* */
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;/* William E. Lamie, Microsoft Corporation */
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;/* */
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;/* DESCRIPTION */
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;/* */
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;/* This function waits for a thread control block pointer to appear in */
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;/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
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;/* in the variable, the corresponding thread is resumed. */
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;/* */
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;/* INPUT */
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;/* */
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;/* None */
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;/* */
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;/* OUTPUT */
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;/* */
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;/* None */
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;/* */
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;/* CALLS */
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;/* */
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;/* None */
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;/* */
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;/* CALLED BY */
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;/* */
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;/* _tx_initialize_kernel_enter ThreadX entry function */
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;/* _tx_thread_system_return Return to system from thread */
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;/* _tx_thread_context_restore Restore thread's context */
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;/* */
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;/* RELEASE HISTORY */
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;/* */
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;/* DATE NAME DESCRIPTION */
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;/* */
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;/* 06-02-2021 William E. Lamie Initial Version 6.1.7 */
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;/* 10-15-2021 William E. Lamie Modified comment(s), and */
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;/* added FPU support, */
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;/* resulting in version 6.1.9 */
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;/* 01-31-2022 William E. Lamie Modified comment(s), */
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;/* resulting in version 6.1.10 */
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;/* 04-25-2022 William E. Lamie Modified comment(s), and */
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;/* added low power support, */
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;/* resulting in version 6.1.11 */
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;/* */
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;/**************************************************************************/
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;VOID _tx_thread_schedule(VOID)
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;{
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.GLB __tx_thread_schedule
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__tx_thread_schedule:
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;
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;
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; /* Wait for a thread to execute. */
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; do
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; {
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MOV.L #__tx_thread_execute_ptr, R1 ; Address of thread to executer ptr
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__tx_thread_schedule_loop:
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SETPSW I ; Enable interrupts
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CLRPSW I ; Disable interrupts
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MOV.L [R1],R2 ; Pickup next thread to execute
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CMP #0,R2 ; Is it NULL?
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BNE __tx_thread_thread_ready ; Not NULL, schedule the thread
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; Idle system - no thread is ready
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.IF TX_LOW_POWER==1
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MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag.
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MOV.L [R1], R2
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ADD #1, R2 ; Disable preemption while enter/exit
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MOV.L R2, [R1]
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BSR _tx_low_power_enter ; Possibly enter low power mode
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.ENDIF
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.IF TX_ENABLE_WAIT==1
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WAIT ; Wait for interrupt
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.ENDIF
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.IF TX_LOW_POWER==1
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CLRPSW I ; Disable interrupts (because WAIT enables interrupts)
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BSR _tx_low_power_exit ; Possibly exit low power mode
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MOV.L #__tx_thread_preempt_disable, R1 ; Load prempt disable flag.
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MOV.L [R1], R2
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SUB #1, R2 ; Enable preemption
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MOV.L R2, [R1]
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MOV.L #__tx_thread_execute_ptr, R1 ; Address of thread to executer ptr
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.ENDIF
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BRA __tx_thread_schedule_loop ; Idle system, keep checking
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__tx_thread_thread_ready:
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;
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; }
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; while(_tx_thread_execute_ptr == TX_NULL);
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;
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; /* Yes! We have a thread to execute. Note that interrupts are locked out at this point. */
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;
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; /* Setup the current thread pointer. */
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; _tx_thread_current_ptr = _tx_thread_execute_ptr;
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;
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MOV.L #__tx_thread_current_ptr, R3
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MOV.L R2,[R3] ; Setup current thread pointer
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;
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; /* Increment the run count for this thread. */
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; _tx_thread_current_ptr -> tx_thread_run_count++;
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;
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MOV.L 4[R2],R3 ; Pickup run count
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ADD #1,R3 ; Increment run counter
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MOV.L R3,4[R2] ; Store it back in control block
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;
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; /* Setup time-slice, if present. */
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; _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
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;
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MOV.L 24[R2],R3 ; Pickup thread time-slice
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MOV.L #__tx_timer_time_slice,R4 ; Pickup pointer to time-slice
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MOV.L R3, [R4] ; Setup time-slice
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;
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; /* Switch to the thread's stack. */
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; SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
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SETPSW U ; User stack mode
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MOV.L 8[R2],R0 ; Pickup stack pointer
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;
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.IF __DPFPU == 1
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MOV.L 144[R2], R1 ; Get tx_thread_fpu_enable.
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CMP #0, R1
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BEQ __tx_thread_schedule_fpu_skip
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DPOPM.L DPSW-DECNT ; Restore FPU register bank if tx_thread_fpu_enable is not 0.
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DPOPM.D DR0-DR15
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__tx_thread_schedule_fpu_skip:
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.ENDIF
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POPM R1-R3 ; Restore accumulators.
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MVTACLO R3, A0
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MVTACHI R2, A0
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MVTACGU R1, A0
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POPM R1-R3
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MVTACLO R3, A1
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MVTACHI R2, A1
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MVTACGU R1, A1
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POPM R6-R13 ; Recover interrupt stack frame
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POPC FPSW
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POPM R14-R15
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POPM R3-R5
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POPM R1-R2
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RTE ; Return to point of interrupt, this restores PC and PSW
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;
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;}
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.GLB __tx_thread_context_save
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.GLB __tx_thread_context_restore
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; Software triggered interrupt used to perform context switches.
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; The priority of this interrupt is set to the lowest priority within
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; tx_initialize_low_level() and triggered by ThreadX when calling
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; _tx_thread_system_return().
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.RVECTOR 27, _tx_software_interrupt_entry
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.GLB _tx_software_interrupt_entry
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_tx_software_interrupt_entry:
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PUSHM R1-R2
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BSR __tx_thread_context_save
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BRA __tx_thread_context_restore
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; Enable saving of DFPU registers for the current thread.
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; If DPFU op are disabled do nothing.
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.GLB _tx_thread_fpu_enable
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_tx_thread_fpu_enable:
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.IF __DPFPU == 1
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PUSHM R1-R4
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MVFC PSW, R2 ; Save PSW to R2
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CLRPSW I ; Lockout interrupts
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MOV.L #__tx_thread_current_ptr, R4
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MOV.L [R4], R1 ; Fetch current thread pointer
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MOV.L #1, R3
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MOV.L R3, 144[R1] ; Set tx_thread_fpu_enable to 1.
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__tx_thread_fpu_enable_exit:
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MVTC R2, PSW ; Restore interrupt status
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POPM R1-R4
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.ENDIF
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RTS
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; Disable saving of DFPU registers for the current thread.
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; If DPFU op are disabled do nothing.
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.GLB _tx_thread_fpu_disable
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_tx_thread_fpu_disable:
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.IF __DPFPU == 1
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PUSHM R1-R4
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MVFC PSW, R2 ; Save PSW to R2
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CLRPSW I ; Lockout interrupts
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MOV.L #__tx_thread_current_ptr, R4
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MOV.L [R4], R1 ; Fetch current thread pointer
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MOV.L #1, R3
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MOV.L R3, 144[R1] ; Set tx_thread_fpu_enable to 1.
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__tx_thread_fpu_disable_exit:
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MVTC R2, PSW ; Restore interrupt status
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POPM R1-R4
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.ENDIF
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RTS
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.END
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