2aa19f3de0
cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack
207 lines
9.6 KiB
ArmAsm
207 lines
9.6 KiB
ArmAsm
@/**************************************************************************/
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@/* */
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@/* Copyright (c) Microsoft Corporation. All rights reserved. */
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@/* */
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@/* This software is licensed under the Microsoft Software License */
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@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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@/* and in the root directory of this software. */
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@/* */
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@/**************************************************************************/
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@
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@
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@/**************************************************************************/
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@/**************************************************************************/
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@/** */
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@/** ThreadX Component */
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@/** */
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@/** Thread */
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@/** */
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@/**************************************************************************/
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@/**************************************************************************/
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#ifdef TX_INCLUDE_USER_DEFINE_FILE
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#include "tx_user.h"
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#endif
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#ifdef TX_ENABLE_FIQ_SUPPORT
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DISABLE_INTS = 0xC0 @ IRQ & FIQ interrupts disabled
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#else
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DISABLE_INTS = 0x80 @ IRQ interrupts disabled
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#endif
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@
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.global _tx_thread_system_state
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.global _tx_thread_current_ptr
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.global _tx_irq_processing_return
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.global _tx_execution_isr_enter
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@
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@
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@/* No 16-bit Thumb mode veneer code is needed for _tx_thread_context_save
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@ since it will never be called 16-bit mode. */
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@
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.arm
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.text
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.align 2
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@/**************************************************************************/
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@/* */
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@/* FUNCTION RELEASE */
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@/* */
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@/* _tx_thread_context_save ARM11/GNU */
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@/* 6.2.1 */
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@/* AUTHOR */
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@/* */
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@/* William E. Lamie, Microsoft Corporation */
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@/* */
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@/* DESCRIPTION */
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@/* */
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@/* This function saves the context of an executing thread in the */
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@/* beginning of interrupt processing. The function also ensures that */
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@/* the system stack is used upon return to the calling ISR. */
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@/* */
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@/* INPUT */
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@/* */
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@/* None */
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@/* */
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@/* OUTPUT */
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@/* */
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@/* None */
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@/* */
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@/* CALLS */
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@/* */
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@/* None */
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@/* */
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@/* CALLED BY */
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@/* */
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@/* ISRs */
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@/* */
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@/* RELEASE HISTORY */
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@/* */
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@/* DATE NAME DESCRIPTION */
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@/* */
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@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
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@/* 03-08-2023 Cindy Deng Modified comment(s), added */
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@/* #include tx_user.h, */
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@/* resulting in version 6.2.1 */
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@/* */
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@/**************************************************************************/
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@VOID _tx_thread_context_save(VOID)
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@{
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.global _tx_thread_context_save
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.type _tx_thread_context_save,function
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_tx_thread_context_save:
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@
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@ /* Upon entry to this routine, it is assumed that IRQ interrupts are locked
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@ out, we are in IRQ mode, and all registers are intact. */
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@
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@ /* Check for a nested interrupt condition. */
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@ if (_tx_thread_system_state++)
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@ {
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@
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STMDB sp!, {r0-r3} @ Save some working registers
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#ifdef TX_ENABLE_FIQ_SUPPORT
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MRS r0, CPSR @ Pickup the CPSR
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ORR r0, r0, #DISABLE_INTS @ Build disable interrupt CPSR
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MSR CPSR_cxsf, r0 @ Disable interrupts
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#endif
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LDR r3, =_tx_thread_system_state @ Pickup address of system state variable
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LDR r2, [r3] @ Pickup system state
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CMP r2, #0 @ Is this the first interrupt?
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BEQ __tx_thread_not_nested_save @ Yes, not a nested context save
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@
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@ /* Nested interrupt condition. */
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@
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ADD r2, r2, #1 @ Increment the interrupt counter
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STR r2, [r3] @ Store it back in the variable
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@
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@ /* Save the rest of the scratch registers on the stack and return to the
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@ calling ISR. */
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@
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MRS r0, SPSR @ Pickup saved SPSR
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SUB lr, lr, #4 @ Adjust point of interrupt
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STMDB sp!, {r0, r10, r12, lr} @ Store other registers
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@
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@ /* Return to the ISR. */
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@
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MOV r10, #0 @ Clear stack limit
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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@
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@ /* Call the ISR enter function to indicate an ISR is executing. */
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@
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PUSH {lr} @ Save ISR lr
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BL _tx_execution_isr_enter @ Call the ISR enter function
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POP {lr} @ Recover ISR lr
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#endif
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B __tx_irq_processing_return @ Continue IRQ processing
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@
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__tx_thread_not_nested_save:
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@ }
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@
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@ /* Otherwise, not nested, check to see if a thread was running. */
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@ else if (_tx_thread_current_ptr)
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@ {
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@
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ADD r2, r2, #1 @ Increment the interrupt counter
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STR r2, [r3] @ Store it back in the variable
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LDR r1, =_tx_thread_current_ptr @ Pickup address of current thread ptr
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LDR r0, [r1] @ Pickup current thread pointer
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CMP r0, #0 @ Is it NULL?
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BEQ __tx_thread_idle_system_save @ If so, interrupt occurred in
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@ scheduling loop - nothing needs saving!
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@
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@ /* Save minimal context of interrupted thread. */
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@
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MRS r2, SPSR @ Pickup saved SPSR
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SUB lr, lr, #4 @ Adjust point of interrupt
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STMDB sp!, {r2, r10, r12, lr} @ Store other registers
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@
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@ /* Save the current stack pointer in the thread's control block. */
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@ _tx_thread_current_ptr -> tx_thread_stack_ptr = sp;
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@
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@ /* Switch to the system stack. */
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@ sp = _tx_thread_system_stack_ptr@
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@
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MOV r10, #0 @ Clear stack limit
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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@
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@ /* Call the ISR enter function to indicate an ISR is executing. */
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@
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PUSH {lr} @ Save ISR lr
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BL _tx_execution_isr_enter @ Call the ISR enter function
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POP {lr} @ Recover ISR lr
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#endif
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B __tx_irq_processing_return @ Continue IRQ processing
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@
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@ }
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@ else
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@ {
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@
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__tx_thread_idle_system_save:
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@
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@ /* Interrupt occurred in the scheduling loop. */
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@
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@ /* Not much to do here, just adjust the stack pointer, and return to IRQ
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@ processing. */
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@
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MOV r10, #0 @ Clear stack limit
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#ifdef TX_ENABLE_EXECUTION_CHANGE_NOTIFY
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@
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@ /* Call the ISR enter function to indicate an ISR is executing. */
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@
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PUSH {lr} @ Save ISR lr
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BL _tx_execution_isr_enter @ Call the ISR enter function
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POP {lr} @ Recover ISR lr
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#endif
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ADD sp, sp, #16 @ Recover saved registers
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B __tx_irq_processing_return @ Continue IRQ processing
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@
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@ }
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@}
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