2aa19f3de0
cee19603d Include tx_user.h conditionally. e40e08007 Update owners d69641273 Update release date and version 394aee52f Add tx_user.h to GNU port assembly files 5cca2ddd0 RISC-V 64 bit port for Microchip e0f2c373c Link Winmm.lib that required by the high-resolution timer. 6af472a68 Update Win32 port with high resolution timer. aea7b556a Add DMB ISH barrier inst in ARMv8-A SMP scheduler 19091a262 Add .section .preamble to m3 m4 m7 module ports ced60e1b7 Add missing parenthesis in ports assembly file 309dc77ca Modules Cortex-A7 IAR new port c752a4063 Modules Cortex-A7 GNU new port dc224b90f Fix race condition in tx_thread_wait_abort and update regression test 6e261f5b7 create threadx cmsis-pack
176 lines
9.6 KiB
ArmAsm
176 lines
9.6 KiB
ArmAsm
@/**************************************************************************/
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@/* */
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@/* Copyright (c) Microsoft Corporation. All rights reserved. */
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@/* */
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@/* This software is licensed under the Microsoft Software License */
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@/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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@/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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@/* and in the root directory of this software. */
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@/* */
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@/**************************************************************************/
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@
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@
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@/**************************************************************************/
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@/**************************************************************************/
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@/** */
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@/** ThreadX Component */
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@/** */
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@/** Thread */
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@/** */
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@/**************************************************************************/
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@/**************************************************************************/
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#ifdef TX_INCLUDE_USER_DEFINE_FILE
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#include "tx_user.h"
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#endif
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.arm
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SVC_MODE = 0x13 @ SVC mode
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#ifdef TX_ENABLE_FIQ_SUPPORT
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CPSR_MASK = 0xDF @ Mask initial CPSR, IRQ & FIQ interrupts enabled
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#else
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CPSR_MASK = 0x9F @ Mask initial CPSR, IRQ interrupts enabled
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#endif
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@
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@
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@/* Define the 16-bit Thumb mode veneer for _tx_thread_stack_build for
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@ applications calling this function from to 16-bit Thumb mode. */
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@
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.text
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.align 2
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.thumb
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.global $_tx_thread_stack_build
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.type $_tx_thread_stack_build,function
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$_tx_thread_stack_build:
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BX pc @ Switch to 32-bit mode
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NOP @
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.arm
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STMFD sp!, {lr} @ Save return address
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BL _tx_thread_stack_build @ Call _tx_thread_stack_build function
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LDMFD sp!, {lr} @ Recover saved return address
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BX lr @ Return to 16-bit caller
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@
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@
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.text
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.align 2
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@/**************************************************************************/
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@/* */
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@/* FUNCTION RELEASE */
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@/* */
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@/* _tx_thread_stack_build ARM9/GNU */
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@/* 6.2.1 */
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@/* AUTHOR */
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@/* */
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@/* William E. Lamie, Microsoft Corporation */
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@/* */
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@/* DESCRIPTION */
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@/* */
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@/* This function builds a stack frame on the supplied thread's stack. */
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@/* The stack frame results in a fake interrupt return to the supplied */
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@/* function pointer. */
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@/* */
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@/* INPUT */
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@/* */
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@/* thread_ptr Pointer to thread control blk */
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@/* function_ptr Pointer to return function */
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@/* */
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@/* OUTPUT */
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@/* */
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@/* None */
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@/* */
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@/* CALLS */
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@/* */
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@/* None */
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@/* */
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@/* CALLED BY */
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@/* */
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@/* _tx_thread_create Create thread service */
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@/* */
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@/* RELEASE HISTORY */
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@/* */
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@/* DATE NAME DESCRIPTION */
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@/* */
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@/* 09-30-2020 William E. Lamie Initial Version 6.1 */
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@/* 03-08-2023 Cindy Deng Modified comment(s), added */
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@/* #include tx_user.h, */
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@/* resulting in version 6.2.1 */
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@/* */
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@/**************************************************************************/
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@VOID _tx_thread_stack_build(TX_THREAD *thread_ptr, VOID (*function_ptr)(VOID))
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@{
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.global _tx_thread_stack_build
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.type _tx_thread_stack_build,function
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_tx_thread_stack_build:
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@
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@
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@ /* Build a fake interrupt frame. The form of the fake interrupt stack
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@ on the ARM9 should look like the following after it is built:
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@
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@ Stack Top: 1 Interrupt stack frame type
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@ CPSR Initial value for CPSR
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@ a1 (r0) Initial value for a1
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@ a2 (r1) Initial value for a2
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@ a3 (r2) Initial value for a3
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@ a4 (r3) Initial value for a4
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@ v1 (r4) Initial value for v1
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@ v2 (r5) Initial value for v2
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@ v3 (r6) Initial value for v3
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@ v4 (r7) Initial value for v4
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@ v5 (r8) Initial value for v5
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@ sb (r9) Initial value for sb
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@ sl (r10) Initial value for sl
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@ fp (r11) Initial value for fp
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@ ip (r12) Initial value for ip
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@ lr (r14) Initial value for lr
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@ pc (r15) Initial value for pc
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@ 0 For stack backtracing
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@
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@ Stack Bottom: (higher memory address) */
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@
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LDR r2, [r0, #16] @ Pickup end of stack area
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BIC r2, r2, #7 @ Ensure 8-byte alignment
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SUB r2, r2, #76 @ Allocate space for the stack frame
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@
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@ /* Actually build the stack frame. */
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@
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MOV r3, #1 @ Build interrupt stack type
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STR r3, [r2, #0] @ Store stack type
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MOV r3, #0 @ Build initial register value
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STR r3, [r2, #8] @ Store initial r0
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STR r3, [r2, #12] @ Store initial r1
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STR r3, [r2, #16] @ Store initial r2
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STR r3, [r2, #20] @ Store initial r3
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STR r3, [r2, #24] @ Store initial r4
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STR r3, [r2, #28] @ Store initial r5
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STR r3, [r2, #32] @ Store initial r6
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STR r3, [r2, #36] @ Store initial r7
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STR r3, [r2, #40] @ Store initial r8
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STR r3, [r2, #44] @ Store initial r9
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LDR r3, [r0, #12] @ Pickup stack starting address
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STR r3, [r2, #48] @ Store initial r10 (sl)
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LDR r3,=_tx_thread_schedule @ Pickup address of _tx_thread_schedule for GDB backtrace
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STR r3, [r2, #60] @ Store initial r14 (lr)
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MOV r3, #0 @ Build initial register value
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STR r3, [r2, #52] @ Store initial r11
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STR r3, [r2, #56] @ Store initial r12
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STR r1, [r2, #64] @ Store initial pc
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STR r3, [r2, #68] @ 0 for back-trace
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MRS r1, CPSR @ Pickup CPSR
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BIC r1, r1, #CPSR_MASK @ Mask mode bits of CPSR
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ORR r3, r1, #SVC_MODE @ Build CPSR, SVC mode, interrupts enabled
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STR r3, [r2, #4] @ Store initial CPSR
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@
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@ /* Setup stack pointer. */
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@ thread_ptr -> tx_thread_stack_ptr = r2;
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@
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STR r2, [r0, #8] @ Save stack pointer in thread's
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@ control block
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#ifdef __THUMB_INTERWORK
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BX lr @ Return to caller
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#else
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MOV pc, lr @ Return to caller
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#endif
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@}
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