256 lines
11 KiB
ArmAsm
256 lines
11 KiB
ArmAsm
/**************************************************************************/
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/* */
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/* Copyright (c) Microsoft Corporation. All rights reserved. */
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/* */
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/* This software is licensed under the Microsoft Software License */
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/* Terms for Microsoft Azure RTOS. Full text of the license can be */
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/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
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/* and in the root directory of this software. */
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/* */
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/**************************************************************************/
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/**************************************************************************/
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/* Copyright (c) Cadence Design Systems, Inc. */
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/* */
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/* Permission is hereby granted, free of charge, to any person obtaining */
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/* a copy of this software and associated documentation files (the */
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/* "Software"), to deal in the Software without restriction, including */
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/* without limitation the rights to use, copy, modify, merge, publish, */
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/* distribute, sublicense, and/or sell copies of the Software, and to */
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/* permit persons to whom the Software is furnished to do so, subject to */
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/* the following conditions: */
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/* */
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/* The above copyright notice and this permission notice shall be */
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/* included in all copies or substantial portions of the Software. */
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/* */
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/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
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/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
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/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
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/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
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/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
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/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
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/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
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/**************************************************************************/
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/**************************************************************************/
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/**************************************************************************/
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/** */
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/** ThreadX Component */
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/** */
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/** Thread */
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/** */
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/**************************************************************************/
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/**************************************************************************/
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#include "tx_port.h"
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#include "xtensa_rtos.h"
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#include "tx_api_asm.h"
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.text
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/**************************************************************************/
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/* */
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/* DESCRIPTION */
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/* */
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/* This function waits for a thread control block pointer to appear in */
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/* the _tx_thread_execute_ptr variable. Once a thread pointer appears */
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/* in the variable, the corresponding thread is resumed. */
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/* */
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/* RELEASE HISTORY */
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/* */
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/* DATE NAME DESCRIPTION */
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/* */
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/* 12-31-2020 Cadence Design Systems Initial Version 6.1.3 */
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/* 10-31-2022 Scott Larson Updated EPK definitions, */
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/* resulting in version 6.2.0 */
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/* */
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/**************************************************************************/
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// VOID _tx_thread_schedule(VOID)
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// {
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.globl _tx_thread_schedule
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.type _tx_thread_schedule,@function
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.align 4
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_tx_thread_schedule:
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#if XCHAL_HAVE_XEA3
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/* Skip "entry" - nothing to save, never returns. */
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movi a2, PS_STACK_KERNEL | PS_DI /* Set PS.STACK = Kernel and */
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movi a3, PS_STACK_MASK | PS_DI_MASK /* disable interrupts. */
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xps a2, a3
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#ifdef __XTENSA_CALL0_ABI__
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mov a15, a1 /* Dispatch code expects a15 = old SP */
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#endif
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movi a0, _xt_dispatch + 3 /* Jump to dispatch code. It will */
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ret /* check for ready thread or idle */
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/* and handle accordingly. */
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ill /* Should never get back here. */
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#else
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/*
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Note on Windowed ABI:
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Callers of this don't expect it to return to them. Most use 'call0'.
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The only windowed (C) caller is _tx_initialize_kernel_enter().
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There are no args or results to pass. So we don't really care if the
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window gets rotated. We can omit the 'entry' altogether and avoid the
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need for a special "no entry" entrypoint to this function.
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*/
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#ifdef XT_ENABLE_TIMING_TEST_HACK
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/* For timing_test "TS" numbers. INTERNAL USE ONLY. */
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/* Always use CALL0. We may be here with windowing disabled. */
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.extern scheduler_return
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call0 scheduler_return
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#endif
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/*
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Wait for a thread to execute (Idle Loop).
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First ensure interrupts (except hi-pri) are disabled so result
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of reading _tx_thread_execute_ptr can't change before testing.
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While there's no thread ready, enable interrupts and wait in a
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low power state, then disable interrupts and repeat the test.
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*/
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// do
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// {
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movi a3, _tx_thread_execute_ptr
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.L_tx_thread_schedule_loop: /* Idle Loop. */
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XT_INTS_DISABLE(a2) /* disable interrupts if not already */
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l32i a2, a3, 0 /* a2 = _tx_thread_execute_ptr */
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bnez a2, .L_tx_thread_schedule_ready
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waiti 0 /* enable interrupts and wait for */
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/* interrupt in low power state */
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j .L_tx_thread_schedule_loop
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// }
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// while(_tx_thread_execute_ptr == TX_NULL);
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.L_tx_thread_schedule_ready:
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/* Yes! We have a thread to execute. Lockout interrupts and
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transfer control to it. Interrupts are already disabled. */
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/* Setup the current thread pointer. */
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// _tx_thread_current_ptr = _tx_thread_execute_ptr;
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movi a3, _tx_thread_current_ptr
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l32i a0, a2, tx_thread_run_count
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s32i a2, a3, 0 /* a2 = _tx_thread_current_ptr (TCB) */
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/* Increment the run count for this thread. */
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// _tx_thread_current_ptr -> tx_thread_run_count++;
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addi a3, a0, 1
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movi a0, _tx_timer_time_slice
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s32i a3, a2, tx_thread_run_count
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/* Setup time-slice, if present. */
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// _tx_timer_time_slice = _tx_thread_current_ptr -> tx_thread_time_slice;
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l32i a3, a2, tx_thread_time_slice
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s32i a3, a0, 0
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#ifdef TX_THREAD_SAFE_CLIB
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// Load library-specific global context ptr address. */
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#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
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movi a0, _impure_ptr
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#elif XSHAL_CLIB == XTHAL_CLIB_XCLIB
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movi a0, _reent_ptr
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#else
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#error TX_THREAD_SAFE_CLIB defined with unsupported C library.
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#endif
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l32i a3, a2, tx_thread_clib_ptr
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s32i a3, a0, 0 /* point to thread's reent struct */
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#endif
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/* Switch to the thread's stack. */
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// SP = _tx_thread_execute_ptr -> tx_thread_stack_ptr;
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l32i sp, a2, tx_thread_stack_ptr
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#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
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/* Call the thread entry function to indicate the thread is executing. */
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#ifdef __XTENSA_CALL0_ABI__
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call0 _tx_execution_thread_enter
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#else
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call8 _tx_execution_thread_enter
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#endif
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#endif
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/* Determine if an interrupt frame or a synchronous task suspension frame
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is present. */
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l32i a3, a2, tx_thread_solicited
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bnez a3, .L_tx_thread_synch_return
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.Ln_tx_thread_asynch_return:
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#if XCHAL_CP_NUM > 0
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/* Restore thread's CPENABLE (enable co-processors this thread owns). */
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l16ui a3, a2, tx_thread_cp_state + XT_CPENABLE
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wsr a3, CPENABLE
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#endif
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/* Here we return from unsolicited entry with an interrupt stack frame. */
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call0 _xt_context_restore
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/* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
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#ifdef __XTENSA_CALL0_ABI__
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l32i a14, sp, XT_STK_A14
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l32i a15, sp, XT_STK_A15
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#endif
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#if XCHAL_CP_NUM > 0
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rsync /* ensure wsr.CPENABLE has completed */
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#endif
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/*
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This does not return to its caller, but to the selected thread.
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Must return via the exit dispatcher corresponding to the entrypoint
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from which this was called. Interruptee's A0, A1, PS, PC are restored
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and the interrupt stack frame is deallocated in the exit dispatcher.
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*/
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l32i a0, sp, XT_STK_EXIT
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ret
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.L_tx_thread_synch_return:
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/* Here we return from a solicited entry with a solicited stack frame. */
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movi a0, TX_FALSE
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l32i a3, sp, XT_STK_PS
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s32i a0, a2, tx_thread_solicited
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#ifdef __XTENSA_CALL0_ABI__
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l32i a12, sp, XT_STK_A12
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l32i a13, sp, XT_STK_A13
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l32i a14, sp, XT_STK_A14
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l32i a15, sp, XT_STK_A15
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#endif
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l32i a0, sp, XT_STK_PC /* return address */
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#if XCHAL_CP_NUM > 0
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/* CPENABLE should already be clear (it was cleared on entry to kernel). */
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rsync /* ensure wsr.CPENABLE has completed */
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#endif
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wsr a3, PS /* no need to sync PS, delay is OK */
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/* This does not return to its caller, but to the selected thread. */
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#ifdef __XTENSA_CALL0_ABI__
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/* 'addi sp, sp, imm' could turn into 'addmi, addi' sequence and make */
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/* the sp briefly point to an illegal stack location. Avoid that. */
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addi a2, sp, XT_STK_FRMSZ
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mov sp, a2
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ret
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#else
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retw
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#endif
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#endif /* XCHAL_HAVE_XEA3 */
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// }
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