commit
This commit is contained in:
Binary file not shown.
@@ -1,4 +1,820 @@
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FILE_TYPE=LIBRARY_PARTS;
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primitive 'CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q';
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pin
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'\TEST\':
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PIN_NUMBER='(0,0,0,0,17)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\NC9\':
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PIN_NUMBER='(0,0,0,0,30)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC8\':
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PIN_NUMBER='(0,0,0,0,10)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC7\':
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PIN_NUMBER='(0,0,0,0,9)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC6\':
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PIN_NUMBER='(0,0,0,0,8)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC5\':
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PIN_NUMBER='(0,0,0,0,7)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC4\':
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PIN_NUMBER='(0,0,0,0,6)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC3\':
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PIN_NUMBER='(0,0,0,0,5)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC2\':
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PIN_NUMBER='(0,0,0,0,4)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\NC1\':
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PIN_NUMBER='(0,0,0,0,2)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\XO\':
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PIN_NUMBER='(0,0,0,28,0)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\XI\':
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PIN_NUMBER='(0,0,0,29,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\UD-\':
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PIN_NUMBER='(0,0,32,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\UD+\':
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PIN_NUMBER='(0,0,31,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\RST#\':
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PIN_NUMBER='(0,0,38,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\ISP\':
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PIN_NUMBER='(0,0,37,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\TXD3\':
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PIN_NUMBER='(0,41,0,0,0)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TXD2\':
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PIN_NUMBER='(0,43,0,0,0)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TXD1\':
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PIN_NUMBER='(0,45,0,0,0)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TXD0\':
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PIN_NUMBER='(0,19,0,0,0)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TNOW3/GPIO11\':
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PIN_NUMBER='(0,47,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TNOW2/GPIO8\':
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PIN_NUMBER='(0,46,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TNOW1/GPIO5\':
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PIN_NUMBER='(0,39,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\TNOW0/GPIO2\':
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PIN_NUMBER='(0,36,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\RXD3\':
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PIN_NUMBER='(0,40,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\RXD2\':
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PIN_NUMBER='(0,42,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\RXD1\':
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PIN_NUMBER='(0,44,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\RXD0\':
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PIN_NUMBER='(0,22,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\RTS3/GPIO10\':
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PIN_NUMBER='(0,16,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\RTS2/GPIO7\':
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PIN_NUMBER='(0,14,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\RTS1/GPIO4\':
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PIN_NUMBER='(0,12,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\RTS0/GPIO1\':
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PIN_NUMBER='(0,20,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\RI0\':
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PIN_NUMBER='(0,24,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\DTR0\':
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PIN_NUMBER='(0,21,0,0,0)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\DSR0\':
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PIN_NUMBER='(0,25,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\DCD0\':
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PIN_NUMBER='(0,23,0,0,0)';
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INPUT_LOAD='(-0.01,0.01)';
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'\CTS3/GPIO9\':
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PIN_NUMBER='(0,15,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\CTS2/GPIO6\':
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PIN_NUMBER='(0,13,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\CTS1/GPIO3\':
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PIN_NUMBER='(0,11,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\CTS0/GPIO0\':
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PIN_NUMBER='(0,26,0,0,0)';
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BIDIRECTIONAL='TRUE';
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INPUT_LOAD='(-0.01,0.01)';
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OUTPUT_LOAD='(1.0,-1.0)';
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'\VIO#48\':
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PIN_NUMBER='(48,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\VIO#2318\':
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PIN_NUMBER='(18,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\VDDK#3\':
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PIN_NUMBER='(3,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\VDDK#35\':
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PIN_NUMBER='(35,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\VCC5\':
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PIN_NUMBER='(27,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\VCC33\':
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PIN_NUMBER='(33,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\GND#34\':
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PIN_NUMBER='(34,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'\GND#1\':
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PIN_NUMBER='(1,0,0,0,0)';
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PINUSE='POWER';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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end_pin;
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body
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PART_NAME='CH9344Q';
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VALUE='CH9344Q';
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BODY_NAME='CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q';
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JEDEC_TYPE='LQFP48_050_700X700';
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PHYS_DES_PREFIX='U';
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CLASS='IC';
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end_body;
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end_primitive;
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primitive 'CAP NP_C0402_DISCRETE_100PF';
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pin
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'2':
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PIN_NUMBER='(2)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'1':
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PIN_NUMBER='(1)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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end_pin;
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body
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PART_NAME='CAP NP';
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VALUE='100pF';
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BODY_NAME='CAP NP_C0402_DISCRETE_100PF';
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JEDEC_TYPE='C0402';
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PHYS_DES_PREFIX='C';
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CLASS='DISCRETE';
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end_body;
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end_primitive;
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primitive 'CAP NP_C0603_DISCRETE_10UF';
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pin
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'2':
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PIN_NUMBER='(2)';
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PINUSE='UNSPEC';
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NO_LOAD_CHECK='Both';
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||||
NO_IO_CHECK='Both';
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NO_ASSERT_CHECK='TRUE';
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NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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'1':
|
||||
PIN_NUMBER='(1)';
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||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
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ALLOW_CONNECT='TRUE';
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end_pin;
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body
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PART_NAME='CAP NP';
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||||
VALUE='10uF';
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BODY_NAME='CAP NP_C0603_DISCRETE_10UF';
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||||
JEDEC_TYPE='C0603';
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||||
PHYS_DES_PREFIX='C';
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||||
CLASS='DISCRETE';
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||||
end_body;
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||||
end_primitive;
|
||||
|
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primitive 'CAP NP_C0402_BGA_DISCRETE_4.7NF';
|
||||
pin
|
||||
'2':
|
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PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='4.7nF';
|
||||
BODY_NAME='CAP NP_C0402_BGA_DISCRETE_4.7NF';
|
||||
JEDEC_TYPE='C0402_BGA';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0402_BGA_DISCRETE_1NF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='1nF';
|
||||
BODY_NAME='CAP NP_C0402_BGA_DISCRETE_1NF';
|
||||
JEDEC_TYPE='C0402_BGA';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0402_BGA_DISCRETE_1UF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='1uF';
|
||||
BODY_NAME='CAP NP_C0402_BGA_DISCRETE_1UF';
|
||||
JEDEC_TYPE='C0402_BGA';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0603_DISCRETE_100NF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='100nF';
|
||||
BODY_NAME='CAP NP_C0603_DISCRETE_100NF';
|
||||
JEDEC_TYPE='C0603';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0402_DISCRETE_1NF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='1nF';
|
||||
BODY_NAME='CAP NP_C0402_DISCRETE_1NF';
|
||||
JEDEC_TYPE='C0402';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0402_DISCRETE_1UF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='1uF';
|
||||
BODY_NAME='CAP NP_C0402_DISCRETE_1UF';
|
||||
JEDEC_TYPE='C0402';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0603_DISCRETE_4.7UF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='4.7uF';
|
||||
BODY_NAME='CAP NP_C0603_DISCRETE_4.7UF';
|
||||
JEDEC_TYPE='C0603';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_C0402_DISCRETE_4.7UF';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP';
|
||||
VALUE='4.7uF';
|
||||
BODY_NAME='CAP NP_C0402_DISCRETE_4.7UF';
|
||||
JEDEC_TYPE='C0402';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'CAP NP_NC_C0402_DISCRETE_10PF/NC';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='CAP NP_NC';
|
||||
VALUE='10pF/NC';
|
||||
BODY_NAME='CAP NP_NC_C0402_DISCRETE_10PF/NC';
|
||||
JEDEC_TYPE='C0402';
|
||||
PHYS_DES_PREFIX='C';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'BEAD_L0603_0R';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='BEAD';
|
||||
VALUE='0R';
|
||||
BODY_NAME='BEAD_L0603_0R';
|
||||
JEDEC_TYPE='L0603';
|
||||
PHYS_DES_PREFIX='FB';
|
||||
CLASS='IC';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'RESISTOR_R0402_DISCRETE_10K';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='RESISTOR';
|
||||
VALUE='10K';
|
||||
BODY_NAME='RESISTOR_R0402_DISCRETE_10K';
|
||||
JEDEC_TYPE='R0402';
|
||||
PHYS_DES_PREFIX='R';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'RESISTOR_R0402_DISCRETE_12.1K';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='RESISTOR';
|
||||
VALUE='12.1K';
|
||||
BODY_NAME='RESISTOR_R0402_DISCRETE_12.1K';
|
||||
JEDEC_TYPE='R0402';
|
||||
PHYS_DES_PREFIX='R';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'RESISTOR_R0402_DISCRETE_0R';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='RESISTOR';
|
||||
VALUE='0R';
|
||||
BODY_NAME='RESISTOR_R0402_DISCRETE_0R';
|
||||
JEDEC_TYPE='R0402';
|
||||
PHYS_DES_PREFIX='R';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'RESISTOR_R0402_DISCRETE_240R';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='RESISTOR';
|
||||
VALUE='240R';
|
||||
BODY_NAME='RESISTOR_R0402_DISCRETE_240R';
|
||||
JEDEC_TYPE='R0402';
|
||||
PHYS_DES_PREFIX='R';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'RESISTOR_NC_R0402_DISCRETE_10K/NC';
|
||||
pin
|
||||
'2':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'1':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='RESISTOR_NC';
|
||||
VALUE='10K/NC';
|
||||
BODY_NAME='RESISTOR_NC_R0402_DISCRETE_10K/NC';
|
||||
JEDEC_TYPE='R0402';
|
||||
PHYS_DES_PREFIX='R';
|
||||
CLASS='DISCRETE';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'MMCX-180_MMCX-180_50OHM';
|
||||
pin
|
||||
'\SIG\':
|
||||
PIN_NUMBER='(1)';
|
||||
PINUSE='UNSPEC';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'\GND#5\':
|
||||
PIN_NUMBER='(5)';
|
||||
PINUSE='POWER';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'\GND#4\':
|
||||
PIN_NUMBER='(4)';
|
||||
PINUSE='POWER';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'\GND#3\':
|
||||
PIN_NUMBER='(3)';
|
||||
PINUSE='POWER';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
'\GND#2\':
|
||||
PIN_NUMBER='(2)';
|
||||
PINUSE='POWER';
|
||||
NO_LOAD_CHECK='Both';
|
||||
NO_IO_CHECK='Both';
|
||||
NO_ASSERT_CHECK='TRUE';
|
||||
NO_DIR_CHECK='TRUE';
|
||||
ALLOW_CONNECT='TRUE';
|
||||
end_pin;
|
||||
body
|
||||
PART_NAME='MMCX-180';
|
||||
VALUE='50Ohm';
|
||||
BODY_NAME='MMCX-180_MMCX-180_50OHM';
|
||||
JEDEC_TYPE='MMCX-180';
|
||||
PHYS_DES_PREFIX='J';
|
||||
CLASS='IC';
|
||||
end_body;
|
||||
end_primitive;
|
||||
|
||||
primitive 'TLV62569DBVR_SOT_23_5_TLV62569DBV';
|
||||
pin
|
||||
'\VIN\':
|
||||
|
||||
Binary file not shown.
Binary file not shown.
+78
-3
@@ -1,5 +1,60 @@
|
||||
A!REFDES!COMP_REUSE_ID!COMP_SIGNAL_MODEL!COMP_NO_XNET_CONNECTION!COMP_PARENT_PPT!COMP_SYMBOL_EDITED!COMP_PARENT_PPT_PART!COMP_EMBEDDED_PLACEMENT!COMP_RKO_NUM_LAYERS!COMP_RKO_SHORT_SIDE_OVERSIZE!COMP_RKO_LONG_SIDE_OVERSIZE!COMP_RKO_REF_LAYER!COMP_ASI_MODEL!
|
||||
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
|
||||
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Sat Aug 15 10:52:42 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
|
||||
S!U19!!!!!!!!!!!!!
|
||||
S!C11!!!!!!!!!!!!!
|
||||
S!C12!!!!!!!!!!!!!
|
||||
S!C28!!!!!!!!!!!!!
|
||||
S!C14!!!!!!!!!!!!!
|
||||
S!C29!!!!!!!!!!!!!
|
||||
S!C30!!!!!!!!!!!!!
|
||||
S!C31!!!!!!!!!!!!!
|
||||
S!C17!!!!!!!!!!!!!
|
||||
S!C18!!!!!!!!!!!!!
|
||||
S!C19!!!!!!!!!!!!!
|
||||
S!C20!!!!!!!!!!!!!
|
||||
S!C21!!!!!!!!!!!!!
|
||||
S!C22!!!!!!!!!!!!!
|
||||
S!C23!!!!!!!!!!!!!
|
||||
S!C24!!!!!!!!!!!!!
|
||||
S!C25!!!!!!!!!!!!!
|
||||
S!C26!!!!!!!!!!!!!
|
||||
S!C27!!!!!!!!!!!!!
|
||||
S!C32!!!!!!!!!!!!!
|
||||
S!C43!!!!!!!!!!!!!
|
||||
S!C53!!!!!!!!!!!!!
|
||||
S!C62!!!!!!!!!!!!!
|
||||
S!C46!!!!!!!!!!!!!
|
||||
S!C48!!!!!!!!!!!!!
|
||||
S!C51!!!!!!!!!!!!!
|
||||
S!C55!!!!!!!!!!!!!
|
||||
S!C58!!!!!!!!!!!!!
|
||||
S!C61!!!!!!!!!!!!!
|
||||
S!C63!!!!!!!!!!!!!
|
||||
S!FB1!!!!!!!!!!!!!
|
||||
S!FB2!!!!!!!!!!!!!
|
||||
S!R10!!!!!!!!!!!!!
|
||||
S!R11!!!!!!!!!!!!!
|
||||
S!R12!!!!!!!!!!!!!
|
||||
S!R14!!!!!!!!!!!!!
|
||||
S!R16!!!!!!!!!!!!!
|
||||
S!R17!!!!!!!!!!!!!
|
||||
S!R19!!!!!!!!!!!!!
|
||||
S!R20!!!!!!!!!!!!!
|
||||
S!R21!!!!!!!!!!!!!
|
||||
S!R13!!!!!!!!!!!!!
|
||||
S!R7!!!!!!!!!!!!!
|
||||
S!R15!!!!!!!!!!!!!
|
||||
S!R18!!!!!!!!!!!!!
|
||||
S!R2!!!!!!!!!!!!!
|
||||
S!R3!!!!!!!!!!!!!
|
||||
S!R4!!!!!!!!!!!!!
|
||||
S!R5!!!!!!!!!!!!!
|
||||
S!R6!!!!!!!!!!!!!
|
||||
S!R23!!!!!!!!!!!!!
|
||||
S!R24!!!!!!!!!!!!!
|
||||
S!R25!!!!!!!!!!!!!
|
||||
S!J2!!!!!!!!!!!!!
|
||||
S!J3!!!!!!!!!!!!!
|
||||
S!U11!!!!!!!!!!!!!
|
||||
S!U12!!!!!!!!!!!!!
|
||||
S!U13!!!!!!!!!!!!!
|
||||
@@ -11,6 +66,26 @@ S!C1!!!!!!!!!!!!!
|
||||
S!C2!!!!!!!!!!!!!
|
||||
S!C10!!!!!!!!!!!!!
|
||||
S!C9!!!!!!!!!!!!!
|
||||
S!C13!!!!!!!!!!!!!
|
||||
S!C15!!!!!!!!!!!!!
|
||||
S!C16!!!!!!!!!!!!!
|
||||
S!C33!!!!!!!!!!!!!
|
||||
S!C34!!!!!!!!!!!!!
|
||||
S!C35!!!!!!!!!!!!!
|
||||
S!C36!!!!!!!!!!!!!
|
||||
S!C37!!!!!!!!!!!!!
|
||||
S!C42!!!!!!!!!!!!!
|
||||
S!C44!!!!!!!!!!!!!
|
||||
S!C45!!!!!!!!!!!!!
|
||||
S!C47!!!!!!!!!!!!!
|
||||
S!C49!!!!!!!!!!!!!
|
||||
S!C50!!!!!!!!!!!!!
|
||||
S!C52!!!!!!!!!!!!!
|
||||
S!C54!!!!!!!!!!!!!
|
||||
S!C56!!!!!!!!!!!!!
|
||||
S!C57!!!!!!!!!!!!!
|
||||
S!C59!!!!!!!!!!!!!
|
||||
S!C60!!!!!!!!!!!!!
|
||||
S!C3!!!!!!!!!!!!!
|
||||
S!C4!!!!!!!!!!!!!
|
||||
S!C5!!!!!!!!!!!!!
|
||||
@@ -20,7 +95,7 @@ S!C8!!!!!!!!!!!!!
|
||||
S!J1!!!!!!!!!!!!!
|
||||
S!R1!!!!!!!!!!!!!
|
||||
S!U1!!!!!!!!!!!!!
|
||||
S!U2!!!!!!!!!!!!!
|
||||
S!U3!!!!!!!!!!!!!
|
||||
S!U17!!!!!!!!!!!!!
|
||||
S!U18!!!!!!!!!!!!!
|
||||
S!U9!!!!!!!!!!!!!
|
||||
S!X1!!!!!!!!!!!!!
|
||||
|
||||
Binary file not shown.
+114
-35
@@ -1,42 +1,121 @@
|
||||
A!FUNC_LOGICAL_PATH!COMP_DEVICE_TYPE!REFDES!FUNC_PRIM_FILE!COMP_PARENT_PPT!COMP_PARENT_PPT_PART!COMP_PARENT_PART_TYPE!FUNC_SCH_SIZE!FUNC_HAS_FIXED_SIZE!FUNC_DES!FUNC_GROUP!FUNC_ROOM!FUNC_TERM_IDENT!FUNC_CDS_FSP_INSTANCE_ID!FUNC_CDS_FSP_IS_FPGA!FUNC_CDS_FSP_UID!
|
||||
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U11!.\chipsView.dat!!!!!!F8!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U12!.\chipsView.dat!!!!!!F7!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U13!.\chipsView.dat!!!!!!F6!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U14!.\chipsView.dat!!!!!!F5!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U15!.\chipsView.dat!!!!!!F4!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!U16!.\chipsView.dat!!!!!!TF-40!!!!!!!
|
||||
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Sat Aug 15 10:52:42 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16793506\@\QF_IC\.\CH9344QA.Normal\(chips)!CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q!U19!.\chipsView.dat!!!!!!F6!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16793551\@\QF_IC\.\CH9344QB.Normal\(chips)!CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q!U19!.\chipsView.dat!!!!!!TF-127!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16793582\@\QF_IC\.\CH9344QC.Normal\(chips)!CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q!U19!.\chipsView.dat!!!!!!TF-126!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16793591\@\QF_IC\.\CH9344QD.Normal\(chips)!CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q!U19!.\chipsView.dat!!!!!!TF-125!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16793606\@\QF_IC\.\CH9344QE.Normal\(chips)!CH9344Q_LQFP48_050_700X700_(S1+S2+S3+S4+S5)_CH9344Q!U19!.\chipsView.dat!!!!!!TF-124!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS60874\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100PF!C11!.\chipsView.dat!!!!!!F105!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS61194\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100PF!C12!.\chipsView.dat!!!!!!F104!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16780189\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100PF!C28!.\chipsView.dat!!!!!!F103!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS64015\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_10UF!C14!.\chipsView.dat!!!!!!F80!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781112\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_10UF!C29!.\chipsView.dat!!!!!!F79!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781131\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_10UF!C30!.\chipsView.dat!!!!!!F78!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781150\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_10UF!C31!.\chipsView.dat!!!!!!F77!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16774421\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_4.7NF!C17!.\chipsView.dat!!!!!!F76!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16774477\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_1NF!C18!.\chipsView.dat!!!!!!F75!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16774613\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_1UF!C19!.\chipsView.dat!!!!!!F74!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16774705\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_100NF!C20!.\chipsView.dat!!!!!!F73!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16778769\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C21!.\chipsView.dat!!!!!!F72!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16778930\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C22!.\chipsView.dat!!!!!!F71!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16778954\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C23!.\chipsView.dat!!!!!!F70!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16779229\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C24!.\chipsView.dat!!!!!!F69!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16779248\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C25!.\chipsView.dat!!!!!!F68!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16779458\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C26!.\chipsView.dat!!!!!!F67!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16779568\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1NF!C27!.\chipsView.dat!!!!!!F66!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781169\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1UF!C32!.\chipsView.dat!!!!!!F65!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16788606\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1UF!C43!.\chipsView.dat!!!!!!F64!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789896\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1UF!C53!.\chipsView.dat!!!!!!F63!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16792411\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_1UF!C62!.\chipsView.dat!!!!!!F62!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16788776\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_4.7UF!C46!.\chipsView.dat!!!!!!F61!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789021\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_4.7UF!C48!.\chipsView.dat!!!!!!F60!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789838\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_4.7UF!C51!.\chipsView.dat!!!!!!F59!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789946\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_4.7UF!C55!.\chipsView.dat!!!!!!F58!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16791417\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_4.7UF!C58!.\chipsView.dat!!!!!!F56!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16791929\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_4.7UF!C61!.\chipsView.dat!!!!!!F55!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16793157\@\QF_DISCRETE\.\CAP NP_NC.Normal\(chips)!CAP NP_NC_C0402_DISCRETE_10PF/NC!C63!.\chipsView.dat!!!!!!F53!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16790442\@\QF_DISCRETE\.\BEAD.Normal\(chips)!BEAD_L0603_0R!FB1!.\chipsView.dat!!!!!!F50!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16790635\@\QF_DISCRETE\.\BEAD.Normal\(chips)!BEAD_L0603_0R!FB2!.\chipsView.dat!!!!!!F49!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16785432\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R10!.\chipsView.dat!!!!!!F45!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16785470\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R11!.\chipsView.dat!!!!!!F44!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16785611\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R12!.\chipsView.dat!!!!!!F43!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16785670\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R14!.\chipsView.dat!!!!!!F42!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16786089\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R16!.\chipsView.dat!!!!!!F41!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16786101\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R17!.\chipsView.dat!!!!!!F40!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16786347\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R19!.\chipsView.dat!!!!!!F39!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16786363\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R20!.\chipsView.dat!!!!!!F38!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16786462\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_10K!R21!.\chipsView.dat!!!!!!F37!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16785633\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_12.1K!R13!.\chipsView.dat!!!!!!F36!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16784995\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_12.1K!R7!.\chipsView.dat!!!!!!F35!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16785907\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_0R!R15!.\chipsView.dat!!!!!!F34!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16786204\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_0R!R18!.\chipsView.dat!!!!!!F33!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16777695\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_240R!R2!.\chipsView.dat!!!!!!F32!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16779393\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_240R!R3!.\chipsView.dat!!!!!!F31!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16779420\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_240R!R4!.\chipsView.dat!!!!!!F30!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16780784\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_240R!R5!.\chipsView.dat!!!!!!F29!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16780833\@\QF_DISCRETE\.\RESISTOR.Normal\(chips)!RESISTOR_R0402_DISCRETE_240R!R6!.\chipsView.dat!!!!!!F28!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16792656\@\QF_DISCRETE\.\RESISTOR_NC.Normal\(chips)!RESISTOR_NC_R0402_DISCRETE_10K/NC!R23!.\chipsView.dat!!!!!!F27!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16792697\@\QF_DISCRETE\.\RESISTOR_NC.Normal\(chips)!RESISTOR_NC_R0402_DISCRETE_10K/NC!R24!.\chipsView.dat!!!!!!F26!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16792716\@\QF_DISCRETE\.\RESISTOR_NC.Normal\(chips)!RESISTOR_NC_R0402_DISCRETE_10K/NC!R25!.\chipsView.dat!!!!!!F25!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS60593\@\QF_ANT\.\MMCX-180.Normal\(chips)!MMCX-180_MMCX-180_50OHM!J2!.\chipsView.dat!!!!!!F48!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS60619\@\QF_ANT\.\MMCX-180.Normal\(chips)!MMCX-180_MMCX-180_50OHM!J3!.\chipsView.dat!!!!!!F47!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55441\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U11!.\chipsView.dat!!!!!!F16!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55469\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U12!.\chipsView.dat!!!!!!F15!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55497\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U13!.\chipsView.dat!!!!!!F14!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55525\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U14!.\chipsView.dat!!!!!!F13!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55553\@d.s(v)!TLV62569DBVR_SOT_23_5_TLV62569DBV!U15!.\chipsView.dat!!!!!!F12!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS57948\@\QF_IC\.\INAND_EMMC_153_2LA.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!U16!.\chipsView.dat!!!!!!F11!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS58273\@\QF_IC\.\INAND_EMMC_153_2LB.Normal\(chips)!INAND_EMMC_153_2L_BGA153_050_1150X1300_INAND_EMMC_153_2L!U16!.\chipsView.dat!!!!!!TF-39!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!U10!.\chipsView.dat!!!!!!TF-38!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C1!.\chipsView.dat!!!!!!F23!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C2!.\chipsView.dat!!!!!!F22!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS41270\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C10!.\chipsView.dat!!!!!!F21!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40428\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C9!.\chipsView.dat!!!!!!F20!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19878\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C3!.\chipsView.dat!!!!!!F19!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35873\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C4!.\chipsView.dat!!!!!!F18!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35933\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_10UF!C5!.\chipsView.dat!!!!!!F17!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35977\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_22UF!C6!.\chipsView.dat!!!!!!F16!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40356\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!C7!.\chipsView.dat!!!!!!F15!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40392\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!C8!.\chipsView.dat!!!!!!F14!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS55212\@\QF_IC\.\DDR3_16bit.Normal\(chips)!DDR3_16BIT_FBGA96_14R00X11R00X1R20_DDR3_16BIT!U10!.\chipsView.dat!!!!!!F17!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19387\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C1!.\chipsView.dat!!!!!!F109!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19709\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_18PF!C2!.\chipsView.dat!!!!!!F108!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS41270\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C10!.\chipsView.dat!!!!!!F107!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40428\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_10UF!C9!.\chipsView.dat!!!!!!F106!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS63979\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C13!.\chipsView.dat!!!!!!F102!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS69589\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C15!.\chipsView.dat!!!!!!F101!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS69901\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C16!.\chipsView.dat!!!!!!F100!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781188\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C33!.\chipsView.dat!!!!!!F98!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781207\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C34!.\chipsView.dat!!!!!!F97!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781226\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C35!.\chipsView.dat!!!!!!F96!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781245\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C36!.\chipsView.dat!!!!!!F95!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16781264\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C37!.\chipsView.dat!!!!!!F94!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16787638\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C42!.\chipsView.dat!!!!!!F92!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16788730\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C44!.\chipsView.dat!!!!!!F91!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16788748\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C45!.\chipsView.dat!!!!!!F90!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789003\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C47!.\chipsView.dat!!!!!!F89!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789780\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C49!.\chipsView.dat!!!!!!F88!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789810\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C50!.\chipsView.dat!!!!!!F87!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789864\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C52!.\chipsView.dat!!!!!!F86!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16789920\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C54!.\chipsView.dat!!!!!!F85!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16791351\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C56!.\chipsView.dat!!!!!!F84!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16791389\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C57!.\chipsView.dat!!!!!!F83!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16791893\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C59!.\chipsView.dat!!!!!!F82!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16791911\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C60!.\chipsView.dat!!!!!!F81!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19878\@\DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C3!.\chipsView.dat!!!!!!F99!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35873\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_100NF!C4!.\chipsView.dat!!!!!!F93!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35933\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_DISCRETE_10UF!C5!.\chipsView.dat!!!!!!F57!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS35977\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0603_DISCRETE_22UF!C6!.\chipsView.dat!!!!!!F54!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40356\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!C7!.\chipsView.dat!!!!!!F52!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS40392\@\QF_DISCRETE\.\CAP NP.Normal\(chips)!CAP NP_C0402_BGA_DISCRETE_100NF!C8!.\chipsView.dat!!!!!!F51!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS33975\@\B2BCONNECTOR\.\LSHM-140-030-L-DV-A-N-TR.Normal\(chips)!LSHM-140-030-L-DV-A-N-TR_SAMTEC_LSHM-140-030-L-DV-A-N-TR_LSHM-140-030-L-DV-A-N-TR!J1!.\chipsView.dat!!!!!!TF-27!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19332\@\DISCRETE\.\R.Normal\(chips)!R_R0402_DISCRETE_1M!R1!.\chipsView.dat!!!!!!F13!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F12!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19332\@\DISCRETE\.\R.Normal\(chips)!R_R0402_DISCRETE_1M!R1!.\chipsView.dat!!!!!!F46!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS13961\@\LIBRARY\.\SOC_RK3506BA.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F24!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16006\@\LIBRARY\.\SOC_RK3506BB.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-24!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS16199\@\LIBRARY\.\SOC_RK3506BC.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-23!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-22!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-21!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15385\@\LIBRARY\.\SOC_RK3506BD.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F23!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15310\@\LIBRARY\.\SOC_RK3506BE.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F22!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15781\@\LIBRARY\.\SOC_RK3506BF.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-20!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F11!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!TF-18!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F10!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F9!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS20987\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!TF-15!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21054\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U2!.\chipsView.dat!!!!!!F3!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21176\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!TF-13!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS21243\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U3!.\chipsView.dat!!!!!!F2!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F1!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-5!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-4!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52892\@\QF_IC\.\K922D.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-3!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!TF-2!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15156\@\LIBRARY\.\SOC_RK3506BG.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F21!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS15564\@\LIBRARY\.\SOC_RK3506BH.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F20!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14255\@\LIBRARY\.\SOC_RK3506BI.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F19!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS14712\@\LIBRARY\.\SOC_RK3506BJ.Normal\(chips)!SOC_RK3506B_BGA333_13R30X11R30X1R25__SOC_RK3506B!U1!.\chipsView.dat!!!!!!F18!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS71204\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U17!.\chipsView.dat!!!!!!F10!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS71271\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U17!.\chipsView.dat!!!!!!F9!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS71409\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U18!.\chipsView.dat!!!!!!F8!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS71476\@d.s(v)!LAN8720A-CP-ABC_QFN24-6X6_MC_MCH_LAN8720A-CP-ABC!U18!.\chipsView.dat!!!!!!F7!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52680\@\QF_IC\.\K922A.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F5!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52780\@\QF_IC\.\K922B.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F4!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52850\@\QF_IC\.\K922C.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F3!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS52892\@\QF_IC\.\K922D.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F2!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS53122\@\QF_IC\.\K922E.Normal\(chips)!K922_K922_K922!U9!.\chipsView.dat!!!!!!F1!!!!!!!
|
||||
S!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\INS19052\@\OTHER\.\CRYSTAL 1-3_4Pin.Normal\(chips)!CRYSTAL 1-3_4PIN_XTAL3225_CRYSTAL 1-3_4PIN!X1!.\chipsView.dat!!!!!!F0!!!!!!!
|
||||
|
||||
+120
-6
@@ -1,12 +1,126 @@
|
||||
A!NET_NAME!NET_LOGICAL_PATH!NET_VOLTAGE!
|
||||
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Thu Aug 13 15:48:14 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
|
||||
J!D:/POLARIS/RK3506_NAV/rk3506_nav.brd!Sat Aug 15 10:52:42 2026!-100.0000!-100.0000!100.0000!100.0000!0.0001!millimeters!RK3506_NAV!28.800000 mil!4!UP TO DATE!
|
||||
S!VDDK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDK\!1.2V!
|
||||
S!VCC33!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC33\!3.3V!
|
||||
S!VCC5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC5\!3.3V!
|
||||
S!VIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIO\!3.3V!
|
||||
S!DDR3_A7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A7\!!
|
||||
S!DDR3_WEN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_WEN\!!
|
||||
S!DDR3_A4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A4\!!
|
||||
S!DDR3_A9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A9\!!
|
||||
S!DDR3_RASN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_RASN\!!
|
||||
S!DDR3_A12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A12\!!
|
||||
S!DDR3_A15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A15\!!
|
||||
S!ETH_CLK0_25M_OUT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ETH_CLK0_25M_OUT\!!
|
||||
S!DDR3_A14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A14\!!
|
||||
S!DDR3_BA2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_BA2\!!
|
||||
S!DDR3_A6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A6\!!
|
||||
S!DDR3_A2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A2\!!
|
||||
S!RMII0_RST!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RST\!!
|
||||
S!DDR3_ODT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_ODT\!!
|
||||
S!DDR3_A3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A3\!!
|
||||
S!DDR3_BA1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_BA1\!!
|
||||
S!DDR3_CSN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CSN\!!
|
||||
S!VDDIO_RMII0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO_RMII0\!1.8V!
|
||||
S!DDR3_A5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A5\!!
|
||||
S!DDR3_A11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A11\!!
|
||||
S!DDR3_A1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A1\!!
|
||||
S!DDR3_A8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A8\!!
|
||||
S!DDR3_A13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A13\!!
|
||||
S!DDR3_CASN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CASN\!!
|
||||
S!VDDIO_RMII1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO_RMII1\!1.8V!
|
||||
S!DDR3_A10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A10\!!
|
||||
S!DDR3_BA0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_BA0\!!
|
||||
S!N16785709!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785709\!!
|
||||
S!DDR3_RST!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_RST\!!
|
||||
S!DDR3_CLKN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CLKN\!!
|
||||
S!DDR3_A0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_A0\!!
|
||||
S!N16785482!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785482\!!
|
||||
S!N16785446!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785446\!!
|
||||
S!RMII1_RST!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RST\!!
|
||||
S!ETH_CLK1_25M_OUT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ETH_CLK1_25M_OUT\!!
|
||||
S!DDR3_CKE!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CKE\!!
|
||||
S!N16785007!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16785007\!!
|
||||
S!EMMC_RSTN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_RSTN\!!
|
||||
S!VDD_1V8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_1V8\!1.8V!
|
||||
S!N16792429!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16792429\!!
|
||||
S!DDR_D10!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D10\!!
|
||||
S!DDR_D9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D9\!!
|
||||
S!DDR_D7!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D7\!!
|
||||
S!DDR_D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D3\!!
|
||||
S!RMII1_CLK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_CLK\!!
|
||||
S!DDR_D13!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D13\!!
|
||||
S!DDR_D8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D8\!!
|
||||
S!DDR_DM1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DM1\!!
|
||||
S!DDR_D11!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D11\!!
|
||||
S!DDR_DQS1N!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS1N\!!
|
||||
S!DDR_D4!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D4\!!
|
||||
S!DDR_D14!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D14\!!
|
||||
S!DDR_DQS0P!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS0P\!!
|
||||
S!DDR_D15!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D15\!!
|
||||
S!DDR_D0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D0\!!
|
||||
S!DDR_D6!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D6\!!
|
||||
S!DDR_DQS0N!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS0N\!!
|
||||
S!DDR_D12!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D12\!!
|
||||
S!DDR_DQS1P!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DQS1P\!!
|
||||
S!DDR_DM0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_DM0\!!
|
||||
S!DDR_D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D2\!!
|
||||
S!DDR_D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D1\!!
|
||||
S!DDR_D5!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_D5\!!
|
||||
S!GNSS_COM1_TX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM1_TX\!!
|
||||
S!N16780119!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16780119\!!
|
||||
S!DDR3_CLKP!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_CLKP\!!
|
||||
S!GNSS_COM3_RX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM3_RX\!!
|
||||
S!GNSS_COM1_RX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM1_RX\!!
|
||||
S!GNSS_COM2_RX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM2_RX\!!
|
||||
S!VDDCR_RMII1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR_RMII1\!1.2V!
|
||||
S!GNSS_COM3_TX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM3_TX\!!
|
||||
S!GNSS_COM2_TX!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\GNSS_COM2_TX\!!
|
||||
S!PPS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\PPS\!!
|
||||
S!VDD_GNSS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_GNSS\!3.3V!
|
||||
S!ANT2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ANT2\!!
|
||||
S!ANT1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\ANT1\!!
|
||||
S!N61267!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N61267\!!
|
||||
S!N16777370!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16777370\!!
|
||||
S!RMII0_RXDV_CRS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RXDV_CRS\!!
|
||||
S!DDR3_VREF_CA!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_VREF_CA\!0.675V!
|
||||
S!RMII0_MDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_MDIO\!!
|
||||
S!RMII0_MDC!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_MDC\!!
|
||||
S!DDR3_VREF_DQ!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR3_VREF_DQ\!0.675V!
|
||||
S!N61054!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N61054\!!
|
||||
S!RMII0_TXEN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_TXEN\!!
|
||||
S!RMII0_TXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_TXD1\!!
|
||||
S!RMII0_TXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_TXD0\!!
|
||||
S!VDDCR_RMII0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR_RMII0\!1.2V!
|
||||
S!RMII0_CLK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_CLK\!!
|
||||
S!RMII0_RXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RXD1\!!
|
||||
S!RMII0_RXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII0_RXD0\!!
|
||||
S!RMII1_RXDV_CRS!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RXDV_CRS\!!
|
||||
S!RMII1_MDC!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_MDC\!!
|
||||
S!RMII1_TXEN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_TXEN\!!
|
||||
S!RMII1_TXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_TXD1\!!
|
||||
S!RMII1_TXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_TXD0\!!
|
||||
S!RMII1_RXD0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RXD0\!!
|
||||
S!RMII1_RXD1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_RXD1\!!
|
||||
S!RMII1_MDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\RMII1_MDIO\!!
|
||||
S!EMMC_CLK!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_CLK\!!
|
||||
S!VDDA_RMII1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDA_RMII1\!3.3V!
|
||||
S!VCC_DDR!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC_DDR\!1.35V!
|
||||
S!VDDA_RMII0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDA_RMII0\!3.3V!
|
||||
S!VDD_3V3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_3V3\!3.3V!
|
||||
S!EMMC_CMD!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_CMD\!!
|
||||
S!EMMC_D1!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D1\!!
|
||||
S!EMMC_D0!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D0\!!
|
||||
S!EMMC_D3!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D3\!!
|
||||
S!N16786486!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16786486\!!
|
||||
S!EMMC_D2!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_D2\!!
|
||||
S!EMMC_CLKOUT!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\EMMC_CLKOUT\!!
|
||||
S!N16786382!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16786382\!!
|
||||
S!DDR_VREF_DQ!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_VREF_DQ\!!
|
||||
S!DDR_VREF_CA!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\DDR_VREF_CA\!!
|
||||
S!N16786362!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\N16786362\!!
|
||||
S!VIN!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VIN\!5V!
|
||||
S!SW!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\SW\!3.3V!
|
||||
S!VDDCR!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDCR\!1.5V!
|
||||
S!VDD2A!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD2A\!1.5V!
|
||||
S!VDDIO!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDDIO\!3.3!
|
||||
S!VDD1A!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD1A\!3.3V!
|
||||
S!VCC!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC\!3.3V!
|
||||
S!V_BCKP!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\V_BCKP\!3.3V!
|
||||
S!VCC_1V8!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VCC_1V8\!1.5V!
|
||||
S!VDD_0V9!@\RK3506_NAV\.\SCHEMATIC1\(sch_1):\VDD_0V9\!0.9V!
|
||||
|
||||
+783
-581
File diff suppressed because it is too large
Load Diff
Binary file not shown.
@@ -7,66 +7,49 @@
|
||||
"Pin Property" : [],
|
||||
"Component" : [
|
||||
{
|
||||
"Name" : "J2",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips)",
|
||||
"Logical" : "J2",
|
||||
"Name" : "U20",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS16795323\\@\\QF_IC\\.\\CH334P.Normal\\(chips)",
|
||||
"Logical" : "U20",
|
||||
"Physical" : null
|
||||
}
|
||||
],
|
||||
"Net" : [
|
||||
{
|
||||
"Name" : "VDD33",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\VDD33\\",
|
||||
"Logical" : "VDD33",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "EP",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\EP\\",
|
||||
"Logical" : "EP",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J3",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips)",
|
||||
"Logical" : "J3",
|
||||
"Name" : "V5",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\V5\\",
|
||||
"Logical" : "V5",
|
||||
"Physical" : null
|
||||
}
|
||||
],
|
||||
"Net" : [],
|
||||
"Connection" : [
|
||||
{
|
||||
"Name" : "J2.3",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#3\\",
|
||||
"Logical" : "GND",
|
||||
"Name" : "U20.16",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS16795323\\@\\QF_IC\\.\\CH334P.Normal\\(chips):\\VDD33\\",
|
||||
"Logical" : "VDD33",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J2.4",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#4\\",
|
||||
"Logical" : "GND",
|
||||
"Name" : "U20.17",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS16795323\\@\\QF_IC\\.\\CH334P.Normal\\(chips):\\EP\\",
|
||||
"Logical" : "EP",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J2.2",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#2\\",
|
||||
"Logical" : "GND",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J2.5",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60593\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#5\\",
|
||||
"Logical" : "GND",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J3.2",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#2\\",
|
||||
"Logical" : "GND",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J3.3",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#3\\",
|
||||
"Logical" : "GND",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J3.4",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#4\\",
|
||||
"Logical" : "GND",
|
||||
"Physical" : null
|
||||
},
|
||||
{
|
||||
"Name" : "J3.5",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS60619\\@\\QF_ANT\\.\\MMCX-180.Normal\\(chips):\\GND#5\\",
|
||||
"Logical" : "GND",
|
||||
"Name" : "U20.15",
|
||||
"C_PATH" : "@\\RK3506_NAV\\.\\SCHEMATIC1\\(sch_1):\\INS16795323\\@\\QF_IC\\.\\CH334P.Normal\\(chips):\\V5\\",
|
||||
"Logical" : "V5",
|
||||
"Physical" : null
|
||||
}
|
||||
]
|
||||
|
||||
Binary file not shown.
Reference in New Issue
Block a user